mirror of
https://github.com/bkaradzic/bgfx.git
synced 2026-02-17 20:52:36 +01:00
Updated spirv-headers.
This commit is contained in:
Бранимир Караџић
@@ -95,7 +95,8 @@
|
||||
<id value="42" vendor="Rendong Liang" tool="spq" comment="Contact Rendong Liang, admin@penguinliong.moe, https://github.com/PENGUINLIONG/spq-rs"/>
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<id value="43" vendor="LLVM" tool="LLVM SPIR-V Backend" comment="Contact Michal Paszkowski, michal.paszkowski@intel.com, https://github.com/llvm/llvm-project/tree/main/llvm/lib/Target/SPIRV"/>
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||||
<id value="44" vendor="Robert Konrad" tool="Kongruent" comment="Contact Robert Konrad, https://github.com/Kode/Kongruent"/>
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<unused start="45" end="0xFFFF" comment="Tool ID range reservable for future use by vendors"/>
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<id value="45" vendor="Kitsunebi Games" tool="Nuvk SPIR-V Emitter and DLSL compiler" comment="Contact Luna Nielsen, luna@foxgirls.gay, https://github.com/Inochi2D/nuvk"/>
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<unused start="46" end="0xFFFF" comment="Tool ID range reservable for future use by vendors"/>
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</ids>
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<!-- SECTION: SPIR-V Opcodes and Enumerants -->
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@@ -152,13 +153,14 @@
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<ids type="opcode" start="6528" end="6591" vendor="Codeplay" comment="Contact duncan.brawley@codeplay.com"/>
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<ids type="opcode" start="6592" end="6655" vendor="Saarland University" comment="Contact devillers@cg.uni-saarland.de"/>
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<ids type="opcode" start="6656" end="6719" vendor="Meta" comment="Contact dunfanlu@meta.com"/>
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<ids type="opcode" start="6720" end="6783" vendor="MediaTek" comment="Contact samuel.huang@mediatek.com"/>
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<!-- Opcode enumerants to reserve for future use. To get a block, allocate
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multiples of 64 starting at the lowest available point in this
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block and add a corresponding <ids> tag immediately above. Make
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sure to fill in the vendor attribute, and preferably add a contact
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person/address in a comment attribute. -->
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<!-- Example new block: <ids type="opcode" start="XXXX" end="XXXX+64n-1" vendor="Add vendor" comment="Contact TBD"/> -->
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<ids type="opcode" start="6720" end="65535" comment="Opcode range reservable for future use by vendors"/>
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<ids type="opcode" start="6784" end="65535" comment="Opcode range reservable for future use by vendors"/>
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<!-- End reservations of opcodes -->
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@@ -185,13 +187,14 @@
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<ids type="enumerant" start="6528" end="6591" vendor="Codeplay" comment="Contact duncan.brawley@codeplay.com"/>
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<ids type="enumerant" start="6592" end="6655" vendor="Saarland University" comment="Contact devillers@cg.uni-saarland.de"/>
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<ids type="enumerant" start="6656" end="6719" vendor="Meta" comment="Contact dunfanlu@meta.com"/>
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<ids type="enumerant" start="6720" end="6783" vendor="MediaTek" comment="Contact samuel.huang@mediatek.com"/>
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<!-- Enumerants to reserve for future use. To get a block, allocate
|
||||
multiples of 64 starting at the lowest available point in this
|
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block and add a corresponding <ids> tag immediately above. Make
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sure to fill in the vendor attribute, and preferably add a contact
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||||
person/address in a comment attribute. -->
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<!-- Example new block: <ids type="enumerant" start="XXXX" end="XXXX+64n-1" vendor="Add vendor" comment="Contact TBD"/> -->
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<ids type="enumerant" start="6720" end="4294967295" comment="Enumerant range reservable for future use by vendors"/>
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<ids type="enumerant" start="6784" end="4294967295" comment="Enumerant range reservable for future use by vendors"/>
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<!-- End reservations of enumerants -->
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@@ -33,7 +33,7 @@ extern "C" {
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#endif
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enum {
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NonSemanticVkspReflectionRevision = 3,
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NonSemanticVkspReflectionRevision = 4,
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NonSemanticVkspReflectionRevision_BitWidthPadding = 0x7fffffff
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};
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@@ -1,26 +1,26 @@
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{
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"revision" : 3,
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"revision" : 4,
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"instructions" : [
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{
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"opname" : "Configuration",
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"opcode" : 1,
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||||
"operands" : [
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{"kind" : "LiteralString", "name" : "enabledExtensionNames" },
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{"kind" : "LiteralInteger", "name" : "specializationInfoDataSize" },
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||||
{"kind" : "LiteralString", "name" : "specializationInfoData" },
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||||
{"kind" : "LiteralString", "name" : "shaderName" },
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||||
{"kind" : "LiteralString", "name" : "EntryPoint" },
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||||
{"kind" : "LiteralInteger", "name" : "groupCountX" },
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||||
{"kind" : "LiteralInteger", "name" : "groupCountY" },
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||||
{"kind" : "LiteralInteger", "name" : "groupCountZ" },
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{"kind" : "LiteralInteger", "name" : "dispatchId" }
|
||||
{"kind" : "IdRef", "name" : "enabledExtensionNames" },
|
||||
{"kind" : "IdRef", "name" : "specializationInfoDataSize" },
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||||
{"kind" : "IdRef", "name" : "specializationInfoData" },
|
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{"kind" : "IdRef", "name" : "shaderName" },
|
||||
{"kind" : "IdRef", "name" : "EntryPoint" },
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||||
{"kind" : "IdRef", "name" : "groupCountX" },
|
||||
{"kind" : "IdRef", "name" : "groupCountY" },
|
||||
{"kind" : "IdRef", "name" : "groupCountZ" },
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||||
{"kind" : "IdRef", "name" : "dispatchId" }
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]
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},
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||||
{
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||||
"opname" : "StartCounter",
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"opcode" : 2,
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"operands" : [
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||||
{"kind" : "LiteralString", "name" : "name" }
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||||
{"kind" : "IdRef", "name" : "name" }
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||||
]
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||||
},
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{
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@@ -34,104 +34,104 @@
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"opname" : "PushConstants",
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"opcode" : 4,
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"operands" : [
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{ "kind" : "LiteralInteger", "name" : "offset" },
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||||
{ "kind" : "LiteralInteger", "name" : "size" },
|
||||
{ "kind" : "LiteralString", "name" : "pValues" },
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||||
{ "kind" : "LiteralInteger", "name" : "stageFlags" }
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||||
{ "kind" : "IdRef", "name" : "offset" },
|
||||
{ "kind" : "IdRef", "name" : "size" },
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||||
{ "kind" : "IdRef", "name" : "pValues" },
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{ "kind" : "IdRef", "name" : "stageFlags" }
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]
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},
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{
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"opname" : "SpecializationMapEntry",
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"opcode" : 5,
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"operands" : [
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||||
{"kind" : "LiteralInteger", "name" : "constantID" },
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||||
{"kind" : "LiteralInteger", "name" : "offset" },
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||||
{"kind" : "LiteralInteger", "name" : "size" }
|
||||
{"kind" : "IdRef", "name" : "constantID" },
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||||
{"kind" : "IdRef", "name" : "offset" },
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||||
{"kind" : "IdRef", "name" : "size" }
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||||
]
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||||
},
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{
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||||
"opname" : "DescriptorSetBuffer",
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||||
"opcode" : 6,
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||||
"operands" : [
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||||
{ "kind" : "LiteralInteger", "name" : "ds" },
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||||
{ "kind" : "LiteralInteger", "name" : "binding" },
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||||
{ "kind" : "LiteralInteger", "name" : "type" },
|
||||
{ "kind" : "LiteralInteger", "name" : "flags" },
|
||||
{ "kind" : "LiteralInteger", "name" : "queueFamilyIndexCount" },
|
||||
{ "kind" : "LiteralInteger", "name" : "sharingMode" },
|
||||
{ "kind" : "LiteralInteger", "name" : "size" },
|
||||
{ "kind" : "LiteralInteger", "name" : "usage" },
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||||
{ "kind" : "LiteralInteger", "name" : "range" },
|
||||
{ "kind" : "LiteralInteger", "name" : "offset" },
|
||||
{ "kind" : "LiteralInteger", "name" : "memorySize" },
|
||||
{ "kind" : "LiteralInteger", "name" : "memoryType" },
|
||||
{ "kind" : "LiteralInteger", "name" : "bindOffset" },
|
||||
{ "kind" : "LiteralInteger", "name" : "viewFlags" },
|
||||
{ "kind" : "LiteralInteger", "name" : "viewFormat" }
|
||||
{ "kind" : "IdRef", "name" : "ds" },
|
||||
{ "kind" : "IdRef", "name" : "binding" },
|
||||
{ "kind" : "IdRef", "name" : "type" },
|
||||
{ "kind" : "IdRef", "name" : "flags" },
|
||||
{ "kind" : "IdRef", "name" : "queueFamilyIndexCount" },
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||||
{ "kind" : "IdRef", "name" : "sharingMode" },
|
||||
{ "kind" : "IdRef", "name" : "size" },
|
||||
{ "kind" : "IdRef", "name" : "usage" },
|
||||
{ "kind" : "IdRef", "name" : "range" },
|
||||
{ "kind" : "IdRef", "name" : "offset" },
|
||||
{ "kind" : "IdRef", "name" : "memorySize" },
|
||||
{ "kind" : "IdRef", "name" : "memoryType" },
|
||||
{ "kind" : "IdRef", "name" : "bindOffset" },
|
||||
{ "kind" : "IdRef", "name" : "viewFlags" },
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||||
{ "kind" : "IdRef", "name" : "viewFormat" }
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]
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},
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{
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"opname" : "DescriptorSetImage",
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"opcode" : 7,
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"operands" : [
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||||
{ "kind" : "LiteralInteger", "name" : "ds" },
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||||
{ "kind" : "LiteralInteger", "name" : "binding" },
|
||||
{ "kind" : "LiteralInteger", "name" : "type" },
|
||||
{ "kind" : "LiteralInteger", "name" : "imageLayout"},
|
||||
{ "kind" : "LiteralInteger", "name" : "imageFlags"},
|
||||
{ "kind" : "LiteralInteger", "name" : "imageType"},
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||||
{ "kind" : "LiteralInteger", "name" : "imageformat"},
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||||
{ "kind" : "LiteralInteger", "name" : "width"},
|
||||
{ "kind" : "LiteralInteger", "name" : "height"},
|
||||
{ "kind" : "LiteralInteger", "name" : "depth"},
|
||||
{ "kind" : "LiteralInteger", "name" : "mipLevels"},
|
||||
{ "kind" : "LiteralInteger", "name" : "arrayLayers"},
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||||
{ "kind" : "LiteralInteger", "name" : "samples"},
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||||
{ "kind" : "LiteralInteger", "name" : "tiling"},
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||||
{ "kind" : "LiteralInteger", "name" : "usage"},
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||||
{ "kind" : "LiteralInteger", "name" : "sharingMode"},
|
||||
{ "kind" : "LiteralInteger", "name" : "queueFamilyIndexCount"},
|
||||
{ "kind" : "LiteralInteger", "name" : "initialLayout"},
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||||
{ "kind" : "LiteralInteger", "name" : "aspectMask"},
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||||
{ "kind" : "LiteralInteger", "name" : "baseMipLevel"},
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||||
{ "kind" : "LiteralInteger", "name" : "levelCount"},
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||||
{ "kind" : "LiteralInteger", "name" : "baseArrayLayer"},
|
||||
{ "kind" : "LiteralInteger", "name" : "layerCount"},
|
||||
{ "kind" : "LiteralInteger", "name" : "viewFlags"},
|
||||
{ "kind" : "LiteralInteger", "name" : "viewType"},
|
||||
{ "kind" : "LiteralInteger", "name" : "viewFormat"},
|
||||
{ "kind" : "LiteralInteger", "name" : "component_a"},
|
||||
{ "kind" : "LiteralInteger", "name" : "component_b"},
|
||||
{ "kind" : "LiteralInteger", "name" : "component_g"},
|
||||
{ "kind" : "LiteralInteger", "name" : "component_r"},
|
||||
{ "kind" : "LiteralInteger", "name" : "memorySize" },
|
||||
{ "kind" : "LiteralInteger", "name" : "memoryType" },
|
||||
{ "kind" : "LiteralInteger", "name" : "bindOffset"}
|
||||
{ "kind" : "IdRef", "name" : "ds" },
|
||||
{ "kind" : "IdRef", "name" : "binding" },
|
||||
{ "kind" : "IdRef", "name" : "type" },
|
||||
{ "kind" : "IdRef", "name" : "imageLayout"},
|
||||
{ "kind" : "IdRef", "name" : "imageFlags"},
|
||||
{ "kind" : "IdRef", "name" : "imageType"},
|
||||
{ "kind" : "IdRef", "name" : "imageformat"},
|
||||
{ "kind" : "IdRef", "name" : "width"},
|
||||
{ "kind" : "IdRef", "name" : "height"},
|
||||
{ "kind" : "IdRef", "name" : "depth"},
|
||||
{ "kind" : "IdRef", "name" : "mipLevels"},
|
||||
{ "kind" : "IdRef", "name" : "arrayLayers"},
|
||||
{ "kind" : "IdRef", "name" : "samples"},
|
||||
{ "kind" : "IdRef", "name" : "tiling"},
|
||||
{ "kind" : "IdRef", "name" : "usage"},
|
||||
{ "kind" : "IdRef", "name" : "sharingMode"},
|
||||
{ "kind" : "IdRef", "name" : "queueFamilyIndexCount"},
|
||||
{ "kind" : "IdRef", "name" : "initialLayout"},
|
||||
{ "kind" : "IdRef", "name" : "aspectMask"},
|
||||
{ "kind" : "IdRef", "name" : "baseMipLevel"},
|
||||
{ "kind" : "IdRef", "name" : "levelCount"},
|
||||
{ "kind" : "IdRef", "name" : "baseArrayLayer"},
|
||||
{ "kind" : "IdRef", "name" : "layerCount"},
|
||||
{ "kind" : "IdRef", "name" : "viewFlags"},
|
||||
{ "kind" : "IdRef", "name" : "viewType"},
|
||||
{ "kind" : "IdRef", "name" : "viewFormat"},
|
||||
{ "kind" : "IdRef", "name" : "component_a"},
|
||||
{ "kind" : "IdRef", "name" : "component_b"},
|
||||
{ "kind" : "IdRef", "name" : "component_g"},
|
||||
{ "kind" : "IdRef", "name" : "component_r"},
|
||||
{ "kind" : "IdRef", "name" : "memorySize" },
|
||||
{ "kind" : "IdRef", "name" : "memoryType" },
|
||||
{ "kind" : "IdRef", "name" : "bindOffset"}
|
||||
]
|
||||
},
|
||||
{
|
||||
"opname" : "DescriptorSetSampler",
|
||||
"opcode" : 8,
|
||||
"operands" : [
|
||||
{ "kind" : "LiteralInteger", "name" : "ds" },
|
||||
{ "kind" : "LiteralInteger", "name" : "binding" },
|
||||
{ "kind" : "LiteralInteger", "name" : "type" },
|
||||
{ "kind" : "LiteralInteger", "name" : "flags"},
|
||||
{ "kind" : "LiteralInteger", "name" : "magFilter"},
|
||||
{ "kind" : "LiteralInteger", "name" : "minFilter"},
|
||||
{ "kind" : "LiteralInteger", "name" : "mipmapMode"},
|
||||
{ "kind" : "LiteralInteger", "name" : "addressModeU"},
|
||||
{ "kind" : "LiteralInteger", "name" : "addressModeV"},
|
||||
{ "kind" : "LiteralInteger", "name" : "addressModeW"},
|
||||
{ "kind" : "LiteralFloat", "name" : "mipLodBias"},
|
||||
{ "kind" : "LiteralInteger", "name" : "anisotropyEnable"},
|
||||
{ "kind" : "LiteralFloat", "name" : "maxAnisotropy"},
|
||||
{ "kind" : "LiteralInteger", "name" : "compareEnable"},
|
||||
{ "kind" : "LiteralInteger", "name" : "compareOp"},
|
||||
{ "kind" : "LiteralFloat", "name" : "minLod"},
|
||||
{ "kind" : "LiteralFloat", "name" : "maxLod"},
|
||||
{ "kind" : "LiteralInteger", "name" : "borderColor"},
|
||||
{ "kind" : "LiteralInteger", "name" : "unnormalizedCoordinates"}
|
||||
{ "kind" : "IdRef", "name" : "ds" },
|
||||
{ "kind" : "IdRef", "name" : "binding" },
|
||||
{ "kind" : "IdRef", "name" : "type" },
|
||||
{ "kind" : "IdRef", "name" : "flags"},
|
||||
{ "kind" : "IdRef", "name" : "magFilter"},
|
||||
{ "kind" : "IdRef", "name" : "minFilter"},
|
||||
{ "kind" : "IdRef", "name" : "mipmapMode"},
|
||||
{ "kind" : "IdRef", "name" : "addressModeU"},
|
||||
{ "kind" : "IdRef", "name" : "addressModeV"},
|
||||
{ "kind" : "IdRef", "name" : "addressModeW"},
|
||||
{ "kind" : "IdRef", "name" : "mipLodBias"},
|
||||
{ "kind" : "IdRef", "name" : "anisotropyEnable"},
|
||||
{ "kind" : "IdRef", "name" : "maxAnisotropy"},
|
||||
{ "kind" : "IdRef", "name" : "compareEnable"},
|
||||
{ "kind" : "IdRef", "name" : "compareOp"},
|
||||
{ "kind" : "IdRef", "name" : "minLod"},
|
||||
{ "kind" : "IdRef", "name" : "maxLod"},
|
||||
{ "kind" : "IdRef", "name" : "borderColor"},
|
||||
{ "kind" : "IdRef", "name" : "unnormalizedCoordinates"}
|
||||
]
|
||||
}
|
||||
]
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -178,6 +178,7 @@ typedef enum SpvExecutionMode_ {
|
||||
SpvExecutionModeEarlyAndLateFragmentTestsAMD = 5017,
|
||||
SpvExecutionModeStencilRefReplacingEXT = 5027,
|
||||
SpvExecutionModeCoalescingAMDX = 5069,
|
||||
SpvExecutionModeIsApiEntryAMDX = 5070,
|
||||
SpvExecutionModeMaxNodeRecursionAMDX = 5071,
|
||||
SpvExecutionModeStaticNumWorkgroupsAMDX = 5072,
|
||||
SpvExecutionModeShaderIndexAMDX = 5073,
|
||||
@@ -190,11 +191,14 @@ typedef enum SpvExecutionMode_ {
|
||||
SpvExecutionModeStencilRefLessBackAMD = 5084,
|
||||
SpvExecutionModeQuadDerivativesKHR = 5088,
|
||||
SpvExecutionModeRequireFullQuadsKHR = 5089,
|
||||
SpvExecutionModeSharesInputWithAMDX = 5102,
|
||||
SpvExecutionModeOutputLinesEXT = 5269,
|
||||
SpvExecutionModeOutputLinesNV = 5269,
|
||||
SpvExecutionModeOutputPrimitivesEXT = 5270,
|
||||
SpvExecutionModeOutputPrimitivesNV = 5270,
|
||||
SpvExecutionModeDerivativeGroupQuadsKHR = 5289,
|
||||
SpvExecutionModeDerivativeGroupQuadsNV = 5289,
|
||||
SpvExecutionModeDerivativeGroupLinearKHR = 5290,
|
||||
SpvExecutionModeDerivativeGroupLinearNV = 5290,
|
||||
SpvExecutionModeOutputTrianglesEXT = 5298,
|
||||
SpvExecutionModeOutputTrianglesNV = 5298,
|
||||
@@ -241,7 +245,6 @@ typedef enum SpvStorageClass_ {
|
||||
SpvStorageClassStorageBuffer = 12,
|
||||
SpvStorageClassTileImageEXT = 4172,
|
||||
SpvStorageClassNodePayloadAMDX = 5068,
|
||||
SpvStorageClassNodeOutputPayloadAMDX = 5076,
|
||||
SpvStorageClassCallableDataKHR = 5328,
|
||||
SpvStorageClassCallableDataNV = 5328,
|
||||
SpvStorageClassIncomingCallableDataKHR = 5329,
|
||||
@@ -554,6 +557,10 @@ typedef enum SpvDecoration_ {
|
||||
SpvDecorationNodeMaxPayloadsAMDX = 5020,
|
||||
SpvDecorationTrackFinishWritingAMDX = 5078,
|
||||
SpvDecorationPayloadNodeNameAMDX = 5091,
|
||||
SpvDecorationPayloadNodeBaseIndexAMDX = 5098,
|
||||
SpvDecorationPayloadNodeSparseArrayAMDX = 5099,
|
||||
SpvDecorationPayloadNodeArraySizeAMDX = 5100,
|
||||
SpvDecorationPayloadDispatchIndirectAMDX = 5105,
|
||||
SpvDecorationOverrideCoverageNV = 5248,
|
||||
SpvDecorationPassthroughNV = 5250,
|
||||
SpvDecorationViewportRelativeNV = 5252,
|
||||
@@ -717,7 +724,7 @@ typedef enum SpvBuiltIn_ {
|
||||
SpvBuiltInBaryCoordSmoothSampleAMD = 4997,
|
||||
SpvBuiltInBaryCoordPullModelAMD = 4998,
|
||||
SpvBuiltInFragStencilRefEXT = 5014,
|
||||
SpvBuiltInCoalescedInputCountAMDX = 5021,
|
||||
SpvBuiltInRemainingRecursionLevelsAMDX = 5021,
|
||||
SpvBuiltInShaderIndexAMDX = 5073,
|
||||
SpvBuiltInViewportMaskNV = 5253,
|
||||
SpvBuiltInSecondaryPositionNV = 5257,
|
||||
@@ -850,6 +857,7 @@ typedef enum SpvFunctionControlShift_ {
|
||||
SpvFunctionControlDontInlineShift = 1,
|
||||
SpvFunctionControlPureShift = 2,
|
||||
SpvFunctionControlConstShift = 3,
|
||||
SpvFunctionControlOptNoneEXTShift = 16,
|
||||
SpvFunctionControlOptNoneINTELShift = 16,
|
||||
SpvFunctionControlMax = 0x7fffffff,
|
||||
} SpvFunctionControlShift;
|
||||
@@ -860,6 +868,7 @@ typedef enum SpvFunctionControlMask_ {
|
||||
SpvFunctionControlDontInlineMask = 0x00000002,
|
||||
SpvFunctionControlPureMask = 0x00000004,
|
||||
SpvFunctionControlConstMask = 0x00000008,
|
||||
SpvFunctionControlOptNoneEXTMask = 0x00010000,
|
||||
SpvFunctionControlOptNoneINTELMask = 0x00010000,
|
||||
} SpvFunctionControlMask;
|
||||
|
||||
@@ -1109,6 +1118,7 @@ typedef enum SpvCapability_ {
|
||||
SpvCapabilityMeshShadingEXT = 5283,
|
||||
SpvCapabilityFragmentBarycentricKHR = 5284,
|
||||
SpvCapabilityFragmentBarycentricNV = 5284,
|
||||
SpvCapabilityComputeDerivativeGroupQuadsKHR = 5288,
|
||||
SpvCapabilityComputeDerivativeGroupQuadsNV = 5288,
|
||||
SpvCapabilityFragmentDensityEXT = 5291,
|
||||
SpvCapabilityShadingRateNV = 5291,
|
||||
@@ -1146,6 +1156,7 @@ typedef enum SpvCapability_ {
|
||||
SpvCapabilityVulkanMemoryModelDeviceScopeKHR = 5346,
|
||||
SpvCapabilityPhysicalStorageBufferAddresses = 5347,
|
||||
SpvCapabilityPhysicalStorageBufferAddressesEXT = 5347,
|
||||
SpvCapabilityComputeDerivativeGroupLinearKHR = 5350,
|
||||
SpvCapabilityComputeDerivativeGroupLinearNV = 5350,
|
||||
SpvCapabilityRayTracingProvisionalKHR = 5353,
|
||||
SpvCapabilityCooperativeMatrixNV = 5357,
|
||||
@@ -1222,11 +1233,13 @@ typedef enum SpvCapability_ {
|
||||
SpvCapabilityAtomicFloat32AddEXT = 6033,
|
||||
SpvCapabilityAtomicFloat64AddEXT = 6034,
|
||||
SpvCapabilityLongCompositesINTEL = 6089,
|
||||
SpvCapabilityOptNoneEXT = 6094,
|
||||
SpvCapabilityOptNoneINTEL = 6094,
|
||||
SpvCapabilityAtomicFloat16AddEXT = 6095,
|
||||
SpvCapabilityDebugInfoModuleINTEL = 6114,
|
||||
SpvCapabilityBFloat16ConversionINTEL = 6115,
|
||||
SpvCapabilitySplitBarrierINTEL = 6141,
|
||||
SpvCapabilityArithmeticFenceEXT = 6144,
|
||||
SpvCapabilityFPGAClusterAttributesV2INTEL = 6150,
|
||||
SpvCapabilityFPGAKernelAttributesv2INTEL = 6161,
|
||||
SpvCapabilityFPMaxErrorINTEL = 6169,
|
||||
@@ -1846,9 +1859,14 @@ typedef enum SpvOp_ {
|
||||
SpvOpFragmentMaskFetchAMD = 5011,
|
||||
SpvOpFragmentFetchAMD = 5012,
|
||||
SpvOpReadClockKHR = 5056,
|
||||
SpvOpFinalizeNodePayloadsAMDX = 5075,
|
||||
SpvOpAllocateNodePayloadsAMDX = 5074,
|
||||
SpvOpEnqueueNodePayloadsAMDX = 5075,
|
||||
SpvOpTypeNodePayloadArrayAMDX = 5076,
|
||||
SpvOpFinishWritingNodePayloadAMDX = 5078,
|
||||
SpvOpInitializeNodePayloadsAMDX = 5090,
|
||||
SpvOpNodePayloadArrayLengthAMDX = 5090,
|
||||
SpvOpIsNodePayloadValidAMDX = 5101,
|
||||
SpvOpConstantStringAMDX = 5103,
|
||||
SpvOpSpecConstantStringAMDX = 5104,
|
||||
SpvOpGroupNonUniformQuadAllKHR = 5110,
|
||||
SpvOpGroupNonUniformQuadAnyKHR = 5111,
|
||||
SpvOpHitObjectRecordHitMotionNV = 5249,
|
||||
@@ -2166,6 +2184,7 @@ typedef enum SpvOp_ {
|
||||
SpvOpConvertBF16ToFINTEL = 6117,
|
||||
SpvOpControlBarrierArriveINTEL = 6142,
|
||||
SpvOpControlBarrierWaitINTEL = 6143,
|
||||
SpvOpArithmeticFenceEXT = 6145,
|
||||
SpvOpSubgroupBlockPrefetchINTEL = 6221,
|
||||
SpvOpGroupIMulKHR = 6401,
|
||||
SpvOpGroupFMulKHR = 6402,
|
||||
@@ -2597,9 +2616,14 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy
|
||||
case SpvOpFragmentMaskFetchAMD: *hasResult = true; *hasResultType = true; break;
|
||||
case SpvOpFragmentFetchAMD: *hasResult = true; *hasResultType = true; break;
|
||||
case SpvOpReadClockKHR: *hasResult = true; *hasResultType = true; break;
|
||||
case SpvOpFinalizeNodePayloadsAMDX: *hasResult = false; *hasResultType = false; break;
|
||||
case SpvOpAllocateNodePayloadsAMDX: *hasResult = true; *hasResultType = true; break;
|
||||
case SpvOpEnqueueNodePayloadsAMDX: *hasResult = false; *hasResultType = false; break;
|
||||
case SpvOpTypeNodePayloadArrayAMDX: *hasResult = true; *hasResultType = false; break;
|
||||
case SpvOpFinishWritingNodePayloadAMDX: *hasResult = true; *hasResultType = true; break;
|
||||
case SpvOpInitializeNodePayloadsAMDX: *hasResult = false; *hasResultType = false; break;
|
||||
case SpvOpNodePayloadArrayLengthAMDX: *hasResult = true; *hasResultType = true; break;
|
||||
case SpvOpIsNodePayloadValidAMDX: *hasResult = true; *hasResultType = true; break;
|
||||
case SpvOpConstantStringAMDX: *hasResult = true; *hasResultType = false; break;
|
||||
case SpvOpSpecConstantStringAMDX: *hasResult = true; *hasResultType = false; break;
|
||||
case SpvOpGroupNonUniformQuadAllKHR: *hasResult = true; *hasResultType = true; break;
|
||||
case SpvOpGroupNonUniformQuadAnyKHR: *hasResult = true; *hasResultType = true; break;
|
||||
case SpvOpHitObjectRecordHitMotionNV: *hasResult = false; *hasResultType = false; break;
|
||||
@@ -2912,6 +2936,7 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy
|
||||
case SpvOpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break;
|
||||
case SpvOpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
|
||||
case SpvOpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
|
||||
case SpvOpArithmeticFenceEXT: *hasResult = true; *hasResultType = true; break;
|
||||
case SpvOpSubgroupBlockPrefetchINTEL: *hasResult = false; *hasResultType = false; break;
|
||||
case SpvOpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
|
||||
case SpvOpGroupFMulKHR: *hasResult = true; *hasResultType = true; break;
|
||||
@@ -3040,6 +3065,7 @@ inline const char* SpvExecutionModeToString(SpvExecutionMode value) {
|
||||
case SpvExecutionModeEarlyAndLateFragmentTestsAMD: return "EarlyAndLateFragmentTestsAMD";
|
||||
case SpvExecutionModeStencilRefReplacingEXT: return "StencilRefReplacingEXT";
|
||||
case SpvExecutionModeCoalescingAMDX: return "CoalescingAMDX";
|
||||
case SpvExecutionModeIsApiEntryAMDX: return "IsApiEntryAMDX";
|
||||
case SpvExecutionModeMaxNodeRecursionAMDX: return "MaxNodeRecursionAMDX";
|
||||
case SpvExecutionModeStaticNumWorkgroupsAMDX: return "StaticNumWorkgroupsAMDX";
|
||||
case SpvExecutionModeShaderIndexAMDX: return "ShaderIndexAMDX";
|
||||
@@ -3052,10 +3078,11 @@ inline const char* SpvExecutionModeToString(SpvExecutionMode value) {
|
||||
case SpvExecutionModeStencilRefLessBackAMD: return "StencilRefLessBackAMD";
|
||||
case SpvExecutionModeQuadDerivativesKHR: return "QuadDerivativesKHR";
|
||||
case SpvExecutionModeRequireFullQuadsKHR: return "RequireFullQuadsKHR";
|
||||
case SpvExecutionModeSharesInputWithAMDX: return "SharesInputWithAMDX";
|
||||
case SpvExecutionModeOutputLinesEXT: return "OutputLinesEXT";
|
||||
case SpvExecutionModeOutputPrimitivesEXT: return "OutputPrimitivesEXT";
|
||||
case SpvExecutionModeDerivativeGroupQuadsNV: return "DerivativeGroupQuadsNV";
|
||||
case SpvExecutionModeDerivativeGroupLinearNV: return "DerivativeGroupLinearNV";
|
||||
case SpvExecutionModeDerivativeGroupQuadsKHR: return "DerivativeGroupQuadsKHR";
|
||||
case SpvExecutionModeDerivativeGroupLinearKHR: return "DerivativeGroupLinearKHR";
|
||||
case SpvExecutionModeOutputTrianglesEXT: return "OutputTrianglesEXT";
|
||||
case SpvExecutionModePixelInterlockOrderedEXT: return "PixelInterlockOrderedEXT";
|
||||
case SpvExecutionModePixelInterlockUnorderedEXT: return "PixelInterlockUnorderedEXT";
|
||||
@@ -3102,7 +3129,6 @@ inline const char* SpvStorageClassToString(SpvStorageClass value) {
|
||||
case SpvStorageClassStorageBuffer: return "StorageBuffer";
|
||||
case SpvStorageClassTileImageEXT: return "TileImageEXT";
|
||||
case SpvStorageClassNodePayloadAMDX: return "NodePayloadAMDX";
|
||||
case SpvStorageClassNodeOutputPayloadAMDX: return "NodeOutputPayloadAMDX";
|
||||
case SpvStorageClassCallableDataKHR: return "CallableDataKHR";
|
||||
case SpvStorageClassIncomingCallableDataKHR: return "IncomingCallableDataKHR";
|
||||
case SpvStorageClassRayPayloadKHR: return "RayPayloadKHR";
|
||||
@@ -3354,6 +3380,10 @@ inline const char* SpvDecorationToString(SpvDecoration value) {
|
||||
case SpvDecorationNodeMaxPayloadsAMDX: return "NodeMaxPayloadsAMDX";
|
||||
case SpvDecorationTrackFinishWritingAMDX: return "TrackFinishWritingAMDX";
|
||||
case SpvDecorationPayloadNodeNameAMDX: return "PayloadNodeNameAMDX";
|
||||
case SpvDecorationPayloadNodeBaseIndexAMDX: return "PayloadNodeBaseIndexAMDX";
|
||||
case SpvDecorationPayloadNodeSparseArrayAMDX: return "PayloadNodeSparseArrayAMDX";
|
||||
case SpvDecorationPayloadNodeArraySizeAMDX: return "PayloadNodeArraySizeAMDX";
|
||||
case SpvDecorationPayloadDispatchIndirectAMDX: return "PayloadDispatchIndirectAMDX";
|
||||
case SpvDecorationOverrideCoverageNV: return "OverrideCoverageNV";
|
||||
case SpvDecorationPassthroughNV: return "PassthroughNV";
|
||||
case SpvDecorationViewportRelativeNV: return "ViewportRelativeNV";
|
||||
@@ -3507,7 +3537,7 @@ inline const char* SpvBuiltInToString(SpvBuiltIn value) {
|
||||
case SpvBuiltInBaryCoordSmoothSampleAMD: return "BaryCoordSmoothSampleAMD";
|
||||
case SpvBuiltInBaryCoordPullModelAMD: return "BaryCoordPullModelAMD";
|
||||
case SpvBuiltInFragStencilRefEXT: return "FragStencilRefEXT";
|
||||
case SpvBuiltInCoalescedInputCountAMDX: return "CoalescedInputCountAMDX";
|
||||
case SpvBuiltInRemainingRecursionLevelsAMDX: return "RemainingRecursionLevelsAMDX";
|
||||
case SpvBuiltInShaderIndexAMDX: return "ShaderIndexAMDX";
|
||||
case SpvBuiltInViewportMaskNV: return "ViewportMaskNV";
|
||||
case SpvBuiltInSecondaryPositionNV: return "SecondaryPositionNV";
|
||||
@@ -3727,7 +3757,7 @@ inline const char* SpvCapabilityToString(SpvCapability value) {
|
||||
case SpvCapabilityImageFootprintNV: return "ImageFootprintNV";
|
||||
case SpvCapabilityMeshShadingEXT: return "MeshShadingEXT";
|
||||
case SpvCapabilityFragmentBarycentricKHR: return "FragmentBarycentricKHR";
|
||||
case SpvCapabilityComputeDerivativeGroupQuadsNV: return "ComputeDerivativeGroupQuadsNV";
|
||||
case SpvCapabilityComputeDerivativeGroupQuadsKHR: return "ComputeDerivativeGroupQuadsKHR";
|
||||
case SpvCapabilityFragmentDensityEXT: return "FragmentDensityEXT";
|
||||
case SpvCapabilityGroupNonUniformPartitionedNV: return "GroupNonUniformPartitionedNV";
|
||||
case SpvCapabilityShaderNonUniform: return "ShaderNonUniform";
|
||||
@@ -3748,7 +3778,7 @@ inline const char* SpvCapabilityToString(SpvCapability value) {
|
||||
case SpvCapabilityVulkanMemoryModel: return "VulkanMemoryModel";
|
||||
case SpvCapabilityVulkanMemoryModelDeviceScope: return "VulkanMemoryModelDeviceScope";
|
||||
case SpvCapabilityPhysicalStorageBufferAddresses: return "PhysicalStorageBufferAddresses";
|
||||
case SpvCapabilityComputeDerivativeGroupLinearNV: return "ComputeDerivativeGroupLinearNV";
|
||||
case SpvCapabilityComputeDerivativeGroupLinearKHR: return "ComputeDerivativeGroupLinearKHR";
|
||||
case SpvCapabilityRayTracingProvisionalKHR: return "RayTracingProvisionalKHR";
|
||||
case SpvCapabilityCooperativeMatrixNV: return "CooperativeMatrixNV";
|
||||
case SpvCapabilityFragmentShaderSampleInterlockEXT: return "FragmentShaderSampleInterlockEXT";
|
||||
@@ -3819,11 +3849,12 @@ inline const char* SpvCapabilityToString(SpvCapability value) {
|
||||
case SpvCapabilityAtomicFloat32AddEXT: return "AtomicFloat32AddEXT";
|
||||
case SpvCapabilityAtomicFloat64AddEXT: return "AtomicFloat64AddEXT";
|
||||
case SpvCapabilityLongCompositesINTEL: return "LongCompositesINTEL";
|
||||
case SpvCapabilityOptNoneINTEL: return "OptNoneINTEL";
|
||||
case SpvCapabilityOptNoneEXT: return "OptNoneEXT";
|
||||
case SpvCapabilityAtomicFloat16AddEXT: return "AtomicFloat16AddEXT";
|
||||
case SpvCapabilityDebugInfoModuleINTEL: return "DebugInfoModuleINTEL";
|
||||
case SpvCapabilityBFloat16ConversionINTEL: return "BFloat16ConversionINTEL";
|
||||
case SpvCapabilitySplitBarrierINTEL: return "SplitBarrierINTEL";
|
||||
case SpvCapabilityArithmeticFenceEXT: return "ArithmeticFenceEXT";
|
||||
case SpvCapabilityFPGAClusterAttributesV2INTEL: return "FPGAClusterAttributesV2INTEL";
|
||||
case SpvCapabilityFPGAKernelAttributesv2INTEL: return "FPGAKernelAttributesv2INTEL";
|
||||
case SpvCapabilityFPMaxErrorINTEL: return "FPMaxErrorINTEL";
|
||||
@@ -4394,9 +4425,14 @@ inline const char* SpvOpToString(SpvOp value) {
|
||||
case SpvOpFragmentMaskFetchAMD: return "OpFragmentMaskFetchAMD";
|
||||
case SpvOpFragmentFetchAMD: return "OpFragmentFetchAMD";
|
||||
case SpvOpReadClockKHR: return "OpReadClockKHR";
|
||||
case SpvOpFinalizeNodePayloadsAMDX: return "OpFinalizeNodePayloadsAMDX";
|
||||
case SpvOpAllocateNodePayloadsAMDX: return "OpAllocateNodePayloadsAMDX";
|
||||
case SpvOpEnqueueNodePayloadsAMDX: return "OpEnqueueNodePayloadsAMDX";
|
||||
case SpvOpTypeNodePayloadArrayAMDX: return "OpTypeNodePayloadArrayAMDX";
|
||||
case SpvOpFinishWritingNodePayloadAMDX: return "OpFinishWritingNodePayloadAMDX";
|
||||
case SpvOpInitializeNodePayloadsAMDX: return "OpInitializeNodePayloadsAMDX";
|
||||
case SpvOpNodePayloadArrayLengthAMDX: return "OpNodePayloadArrayLengthAMDX";
|
||||
case SpvOpIsNodePayloadValidAMDX: return "OpIsNodePayloadValidAMDX";
|
||||
case SpvOpConstantStringAMDX: return "OpConstantStringAMDX";
|
||||
case SpvOpSpecConstantStringAMDX: return "OpSpecConstantStringAMDX";
|
||||
case SpvOpGroupNonUniformQuadAllKHR: return "OpGroupNonUniformQuadAllKHR";
|
||||
case SpvOpGroupNonUniformQuadAnyKHR: return "OpGroupNonUniformQuadAnyKHR";
|
||||
case SpvOpHitObjectRecordHitMotionNV: return "OpHitObjectRecordHitMotionNV";
|
||||
@@ -4709,6 +4745,7 @@ inline const char* SpvOpToString(SpvOp value) {
|
||||
case SpvOpConvertBF16ToFINTEL: return "OpConvertBF16ToFINTEL";
|
||||
case SpvOpControlBarrierArriveINTEL: return "OpControlBarrierArriveINTEL";
|
||||
case SpvOpControlBarrierWaitINTEL: return "OpControlBarrierWaitINTEL";
|
||||
case SpvOpArithmeticFenceEXT: return "OpArithmeticFenceEXT";
|
||||
case SpvOpSubgroupBlockPrefetchINTEL: return "OpSubgroupBlockPrefetchINTEL";
|
||||
case SpvOpGroupIMulKHR: return "OpGroupIMulKHR";
|
||||
case SpvOpGroupFMulKHR: return "OpGroupFMulKHR";
|
||||
|
||||
@@ -174,6 +174,7 @@ enum class ExecutionMode : unsigned {
|
||||
EarlyAndLateFragmentTestsAMD = 5017,
|
||||
StencilRefReplacingEXT = 5027,
|
||||
CoalescingAMDX = 5069,
|
||||
IsApiEntryAMDX = 5070,
|
||||
MaxNodeRecursionAMDX = 5071,
|
||||
StaticNumWorkgroupsAMDX = 5072,
|
||||
ShaderIndexAMDX = 5073,
|
||||
@@ -186,11 +187,14 @@ enum class ExecutionMode : unsigned {
|
||||
StencilRefLessBackAMD = 5084,
|
||||
QuadDerivativesKHR = 5088,
|
||||
RequireFullQuadsKHR = 5089,
|
||||
SharesInputWithAMDX = 5102,
|
||||
OutputLinesEXT = 5269,
|
||||
OutputLinesNV = 5269,
|
||||
OutputPrimitivesEXT = 5270,
|
||||
OutputPrimitivesNV = 5270,
|
||||
DerivativeGroupQuadsKHR = 5289,
|
||||
DerivativeGroupQuadsNV = 5289,
|
||||
DerivativeGroupLinearKHR = 5290,
|
||||
DerivativeGroupLinearNV = 5290,
|
||||
OutputTrianglesEXT = 5298,
|
||||
OutputTrianglesNV = 5298,
|
||||
@@ -237,7 +241,6 @@ enum class StorageClass : unsigned {
|
||||
StorageBuffer = 12,
|
||||
TileImageEXT = 4172,
|
||||
NodePayloadAMDX = 5068,
|
||||
NodeOutputPayloadAMDX = 5076,
|
||||
CallableDataKHR = 5328,
|
||||
CallableDataNV = 5328,
|
||||
IncomingCallableDataKHR = 5329,
|
||||
@@ -550,6 +553,10 @@ enum class Decoration : unsigned {
|
||||
NodeMaxPayloadsAMDX = 5020,
|
||||
TrackFinishWritingAMDX = 5078,
|
||||
PayloadNodeNameAMDX = 5091,
|
||||
PayloadNodeBaseIndexAMDX = 5098,
|
||||
PayloadNodeSparseArrayAMDX = 5099,
|
||||
PayloadNodeArraySizeAMDX = 5100,
|
||||
PayloadDispatchIndirectAMDX = 5105,
|
||||
OverrideCoverageNV = 5248,
|
||||
PassthroughNV = 5250,
|
||||
ViewportRelativeNV = 5252,
|
||||
@@ -713,7 +720,7 @@ enum class BuiltIn : unsigned {
|
||||
BaryCoordSmoothSampleAMD = 4997,
|
||||
BaryCoordPullModelAMD = 4998,
|
||||
FragStencilRefEXT = 5014,
|
||||
CoalescedInputCountAMDX = 5021,
|
||||
RemainingRecursionLevelsAMDX = 5021,
|
||||
ShaderIndexAMDX = 5073,
|
||||
ViewportMaskNV = 5253,
|
||||
SecondaryPositionNV = 5257,
|
||||
@@ -846,6 +853,7 @@ enum class FunctionControlShift : unsigned {
|
||||
DontInline = 1,
|
||||
Pure = 2,
|
||||
Const = 3,
|
||||
OptNoneEXT = 16,
|
||||
OptNoneINTEL = 16,
|
||||
Max = 0x7fffffff,
|
||||
};
|
||||
@@ -856,6 +864,7 @@ enum class FunctionControlMask : unsigned {
|
||||
DontInline = 0x00000002,
|
||||
Pure = 0x00000004,
|
||||
Const = 0x00000008,
|
||||
OptNoneEXT = 0x00010000,
|
||||
OptNoneINTEL = 0x00010000,
|
||||
};
|
||||
|
||||
@@ -1105,6 +1114,7 @@ enum class Capability : unsigned {
|
||||
MeshShadingEXT = 5283,
|
||||
FragmentBarycentricKHR = 5284,
|
||||
FragmentBarycentricNV = 5284,
|
||||
ComputeDerivativeGroupQuadsKHR = 5288,
|
||||
ComputeDerivativeGroupQuadsNV = 5288,
|
||||
FragmentDensityEXT = 5291,
|
||||
ShadingRateNV = 5291,
|
||||
@@ -1142,6 +1152,7 @@ enum class Capability : unsigned {
|
||||
VulkanMemoryModelDeviceScopeKHR = 5346,
|
||||
PhysicalStorageBufferAddresses = 5347,
|
||||
PhysicalStorageBufferAddressesEXT = 5347,
|
||||
ComputeDerivativeGroupLinearKHR = 5350,
|
||||
ComputeDerivativeGroupLinearNV = 5350,
|
||||
RayTracingProvisionalKHR = 5353,
|
||||
CooperativeMatrixNV = 5357,
|
||||
@@ -1218,11 +1229,13 @@ enum class Capability : unsigned {
|
||||
AtomicFloat32AddEXT = 6033,
|
||||
AtomicFloat64AddEXT = 6034,
|
||||
LongCompositesINTEL = 6089,
|
||||
OptNoneEXT = 6094,
|
||||
OptNoneINTEL = 6094,
|
||||
AtomicFloat16AddEXT = 6095,
|
||||
DebugInfoModuleINTEL = 6114,
|
||||
BFloat16ConversionINTEL = 6115,
|
||||
SplitBarrierINTEL = 6141,
|
||||
ArithmeticFenceEXT = 6144,
|
||||
FPGAClusterAttributesV2INTEL = 6150,
|
||||
FPGAKernelAttributesv2INTEL = 6161,
|
||||
FPMaxErrorINTEL = 6169,
|
||||
@@ -1842,9 +1855,14 @@ enum class Op : unsigned {
|
||||
OpFragmentMaskFetchAMD = 5011,
|
||||
OpFragmentFetchAMD = 5012,
|
||||
OpReadClockKHR = 5056,
|
||||
OpFinalizeNodePayloadsAMDX = 5075,
|
||||
OpAllocateNodePayloadsAMDX = 5074,
|
||||
OpEnqueueNodePayloadsAMDX = 5075,
|
||||
OpTypeNodePayloadArrayAMDX = 5076,
|
||||
OpFinishWritingNodePayloadAMDX = 5078,
|
||||
OpInitializeNodePayloadsAMDX = 5090,
|
||||
OpNodePayloadArrayLengthAMDX = 5090,
|
||||
OpIsNodePayloadValidAMDX = 5101,
|
||||
OpConstantStringAMDX = 5103,
|
||||
OpSpecConstantStringAMDX = 5104,
|
||||
OpGroupNonUniformQuadAllKHR = 5110,
|
||||
OpGroupNonUniformQuadAnyKHR = 5111,
|
||||
OpHitObjectRecordHitMotionNV = 5249,
|
||||
@@ -2162,6 +2180,7 @@ enum class Op : unsigned {
|
||||
OpConvertBF16ToFINTEL = 6117,
|
||||
OpControlBarrierArriveINTEL = 6142,
|
||||
OpControlBarrierWaitINTEL = 6143,
|
||||
OpArithmeticFenceEXT = 6145,
|
||||
OpSubgroupBlockPrefetchINTEL = 6221,
|
||||
OpGroupIMulKHR = 6401,
|
||||
OpGroupFMulKHR = 6402,
|
||||
@@ -2593,9 +2612,14 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
|
||||
case Op::OpFragmentMaskFetchAMD: *hasResult = true; *hasResultType = true; break;
|
||||
case Op::OpFragmentFetchAMD: *hasResult = true; *hasResultType = true; break;
|
||||
case Op::OpReadClockKHR: *hasResult = true; *hasResultType = true; break;
|
||||
case Op::OpFinalizeNodePayloadsAMDX: *hasResult = false; *hasResultType = false; break;
|
||||
case Op::OpAllocateNodePayloadsAMDX: *hasResult = true; *hasResultType = true; break;
|
||||
case Op::OpEnqueueNodePayloadsAMDX: *hasResult = false; *hasResultType = false; break;
|
||||
case Op::OpTypeNodePayloadArrayAMDX: *hasResult = true; *hasResultType = false; break;
|
||||
case Op::OpFinishWritingNodePayloadAMDX: *hasResult = true; *hasResultType = true; break;
|
||||
case Op::OpInitializeNodePayloadsAMDX: *hasResult = false; *hasResultType = false; break;
|
||||
case Op::OpNodePayloadArrayLengthAMDX: *hasResult = true; *hasResultType = true; break;
|
||||
case Op::OpIsNodePayloadValidAMDX: *hasResult = true; *hasResultType = true; break;
|
||||
case Op::OpConstantStringAMDX: *hasResult = true; *hasResultType = false; break;
|
||||
case Op::OpSpecConstantStringAMDX: *hasResult = true; *hasResultType = false; break;
|
||||
case Op::OpGroupNonUniformQuadAllKHR: *hasResult = true; *hasResultType = true; break;
|
||||
case Op::OpGroupNonUniformQuadAnyKHR: *hasResult = true; *hasResultType = true; break;
|
||||
case Op::OpHitObjectRecordHitMotionNV: *hasResult = false; *hasResultType = false; break;
|
||||
@@ -2908,6 +2932,7 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
|
||||
case Op::OpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break;
|
||||
case Op::OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
|
||||
case Op::OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
|
||||
case Op::OpArithmeticFenceEXT: *hasResult = true; *hasResultType = true; break;
|
||||
case Op::OpSubgroupBlockPrefetchINTEL: *hasResult = false; *hasResultType = false; break;
|
||||
case Op::OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
|
||||
case Op::OpGroupFMulKHR: *hasResult = true; *hasResultType = true; break;
|
||||
@@ -3036,6 +3061,7 @@ inline const char* ExecutionModeToString(ExecutionMode value) {
|
||||
case ExecutionModeEarlyAndLateFragmentTestsAMD: return "EarlyAndLateFragmentTestsAMD";
|
||||
case ExecutionModeStencilRefReplacingEXT: return "StencilRefReplacingEXT";
|
||||
case ExecutionModeCoalescingAMDX: return "CoalescingAMDX";
|
||||
case ExecutionModeIsApiEntryAMDX: return "IsApiEntryAMDX";
|
||||
case ExecutionModeMaxNodeRecursionAMDX: return "MaxNodeRecursionAMDX";
|
||||
case ExecutionModeStaticNumWorkgroupsAMDX: return "StaticNumWorkgroupsAMDX";
|
||||
case ExecutionModeShaderIndexAMDX: return "ShaderIndexAMDX";
|
||||
@@ -3048,10 +3074,11 @@ inline const char* ExecutionModeToString(ExecutionMode value) {
|
||||
case ExecutionModeStencilRefLessBackAMD: return "StencilRefLessBackAMD";
|
||||
case ExecutionModeQuadDerivativesKHR: return "QuadDerivativesKHR";
|
||||
case ExecutionModeRequireFullQuadsKHR: return "RequireFullQuadsKHR";
|
||||
case ExecutionModeSharesInputWithAMDX: return "SharesInputWithAMDX";
|
||||
case ExecutionModeOutputLinesEXT: return "OutputLinesEXT";
|
||||
case ExecutionModeOutputPrimitivesEXT: return "OutputPrimitivesEXT";
|
||||
case ExecutionModeDerivativeGroupQuadsNV: return "DerivativeGroupQuadsNV";
|
||||
case ExecutionModeDerivativeGroupLinearNV: return "DerivativeGroupLinearNV";
|
||||
case ExecutionModeDerivativeGroupQuadsKHR: return "DerivativeGroupQuadsKHR";
|
||||
case ExecutionModeDerivativeGroupLinearKHR: return "DerivativeGroupLinearKHR";
|
||||
case ExecutionModeOutputTrianglesEXT: return "OutputTrianglesEXT";
|
||||
case ExecutionModePixelInterlockOrderedEXT: return "PixelInterlockOrderedEXT";
|
||||
case ExecutionModePixelInterlockUnorderedEXT: return "PixelInterlockUnorderedEXT";
|
||||
@@ -3098,7 +3125,6 @@ inline const char* StorageClassToString(StorageClass value) {
|
||||
case StorageClassStorageBuffer: return "StorageBuffer";
|
||||
case StorageClassTileImageEXT: return "TileImageEXT";
|
||||
case StorageClassNodePayloadAMDX: return "NodePayloadAMDX";
|
||||
case StorageClassNodeOutputPayloadAMDX: return "NodeOutputPayloadAMDX";
|
||||
case StorageClassCallableDataKHR: return "CallableDataKHR";
|
||||
case StorageClassIncomingCallableDataKHR: return "IncomingCallableDataKHR";
|
||||
case StorageClassRayPayloadKHR: return "RayPayloadKHR";
|
||||
@@ -3350,6 +3376,10 @@ inline const char* DecorationToString(Decoration value) {
|
||||
case DecorationNodeMaxPayloadsAMDX: return "NodeMaxPayloadsAMDX";
|
||||
case DecorationTrackFinishWritingAMDX: return "TrackFinishWritingAMDX";
|
||||
case DecorationPayloadNodeNameAMDX: return "PayloadNodeNameAMDX";
|
||||
case DecorationPayloadNodeBaseIndexAMDX: return "PayloadNodeBaseIndexAMDX";
|
||||
case DecorationPayloadNodeSparseArrayAMDX: return "PayloadNodeSparseArrayAMDX";
|
||||
case DecorationPayloadNodeArraySizeAMDX: return "PayloadNodeArraySizeAMDX";
|
||||
case DecorationPayloadDispatchIndirectAMDX: return "PayloadDispatchIndirectAMDX";
|
||||
case DecorationOverrideCoverageNV: return "OverrideCoverageNV";
|
||||
case DecorationPassthroughNV: return "PassthroughNV";
|
||||
case DecorationViewportRelativeNV: return "ViewportRelativeNV";
|
||||
@@ -3503,7 +3533,7 @@ inline const char* BuiltInToString(BuiltIn value) {
|
||||
case BuiltInBaryCoordSmoothSampleAMD: return "BaryCoordSmoothSampleAMD";
|
||||
case BuiltInBaryCoordPullModelAMD: return "BaryCoordPullModelAMD";
|
||||
case BuiltInFragStencilRefEXT: return "FragStencilRefEXT";
|
||||
case BuiltInCoalescedInputCountAMDX: return "CoalescedInputCountAMDX";
|
||||
case BuiltInRemainingRecursionLevelsAMDX: return "RemainingRecursionLevelsAMDX";
|
||||
case BuiltInShaderIndexAMDX: return "ShaderIndexAMDX";
|
||||
case BuiltInViewportMaskNV: return "ViewportMaskNV";
|
||||
case BuiltInSecondaryPositionNV: return "SecondaryPositionNV";
|
||||
@@ -3723,7 +3753,7 @@ inline const char* CapabilityToString(Capability value) {
|
||||
case CapabilityImageFootprintNV: return "ImageFootprintNV";
|
||||
case CapabilityMeshShadingEXT: return "MeshShadingEXT";
|
||||
case CapabilityFragmentBarycentricKHR: return "FragmentBarycentricKHR";
|
||||
case CapabilityComputeDerivativeGroupQuadsNV: return "ComputeDerivativeGroupQuadsNV";
|
||||
case CapabilityComputeDerivativeGroupQuadsKHR: return "ComputeDerivativeGroupQuadsKHR";
|
||||
case CapabilityFragmentDensityEXT: return "FragmentDensityEXT";
|
||||
case CapabilityGroupNonUniformPartitionedNV: return "GroupNonUniformPartitionedNV";
|
||||
case CapabilityShaderNonUniform: return "ShaderNonUniform";
|
||||
@@ -3744,7 +3774,7 @@ inline const char* CapabilityToString(Capability value) {
|
||||
case CapabilityVulkanMemoryModel: return "VulkanMemoryModel";
|
||||
case CapabilityVulkanMemoryModelDeviceScope: return "VulkanMemoryModelDeviceScope";
|
||||
case CapabilityPhysicalStorageBufferAddresses: return "PhysicalStorageBufferAddresses";
|
||||
case CapabilityComputeDerivativeGroupLinearNV: return "ComputeDerivativeGroupLinearNV";
|
||||
case CapabilityComputeDerivativeGroupLinearKHR: return "ComputeDerivativeGroupLinearKHR";
|
||||
case CapabilityRayTracingProvisionalKHR: return "RayTracingProvisionalKHR";
|
||||
case CapabilityCooperativeMatrixNV: return "CooperativeMatrixNV";
|
||||
case CapabilityFragmentShaderSampleInterlockEXT: return "FragmentShaderSampleInterlockEXT";
|
||||
@@ -3815,11 +3845,12 @@ inline const char* CapabilityToString(Capability value) {
|
||||
case CapabilityAtomicFloat32AddEXT: return "AtomicFloat32AddEXT";
|
||||
case CapabilityAtomicFloat64AddEXT: return "AtomicFloat64AddEXT";
|
||||
case CapabilityLongCompositesINTEL: return "LongCompositesINTEL";
|
||||
case CapabilityOptNoneINTEL: return "OptNoneINTEL";
|
||||
case CapabilityOptNoneEXT: return "OptNoneEXT";
|
||||
case CapabilityAtomicFloat16AddEXT: return "AtomicFloat16AddEXT";
|
||||
case CapabilityDebugInfoModuleINTEL: return "DebugInfoModuleINTEL";
|
||||
case CapabilityBFloat16ConversionINTEL: return "BFloat16ConversionINTEL";
|
||||
case CapabilitySplitBarrierINTEL: return "SplitBarrierINTEL";
|
||||
case CapabilityArithmeticFenceEXT: return "ArithmeticFenceEXT";
|
||||
case CapabilityFPGAClusterAttributesV2INTEL: return "FPGAClusterAttributesV2INTEL";
|
||||
case CapabilityFPGAKernelAttributesv2INTEL: return "FPGAKernelAttributesv2INTEL";
|
||||
case CapabilityFPMaxErrorINTEL: return "FPMaxErrorINTEL";
|
||||
@@ -4390,9 +4421,14 @@ inline const char* OpToString(Op value) {
|
||||
case OpFragmentMaskFetchAMD: return "OpFragmentMaskFetchAMD";
|
||||
case OpFragmentFetchAMD: return "OpFragmentFetchAMD";
|
||||
case OpReadClockKHR: return "OpReadClockKHR";
|
||||
case OpFinalizeNodePayloadsAMDX: return "OpFinalizeNodePayloadsAMDX";
|
||||
case OpAllocateNodePayloadsAMDX: return "OpAllocateNodePayloadsAMDX";
|
||||
case OpEnqueueNodePayloadsAMDX: return "OpEnqueueNodePayloadsAMDX";
|
||||
case OpTypeNodePayloadArrayAMDX: return "OpTypeNodePayloadArrayAMDX";
|
||||
case OpFinishWritingNodePayloadAMDX: return "OpFinishWritingNodePayloadAMDX";
|
||||
case OpInitializeNodePayloadsAMDX: return "OpInitializeNodePayloadsAMDX";
|
||||
case OpNodePayloadArrayLengthAMDX: return "OpNodePayloadArrayLengthAMDX";
|
||||
case OpIsNodePayloadValidAMDX: return "OpIsNodePayloadValidAMDX";
|
||||
case OpConstantStringAMDX: return "OpConstantStringAMDX";
|
||||
case OpSpecConstantStringAMDX: return "OpSpecConstantStringAMDX";
|
||||
case OpGroupNonUniformQuadAllKHR: return "OpGroupNonUniformQuadAllKHR";
|
||||
case OpGroupNonUniformQuadAnyKHR: return "OpGroupNonUniformQuadAnyKHR";
|
||||
case OpHitObjectRecordHitMotionNV: return "OpHitObjectRecordHitMotionNV";
|
||||
@@ -4705,6 +4741,7 @@ inline const char* OpToString(Op value) {
|
||||
case OpConvertBF16ToFINTEL: return "OpConvertBF16ToFINTEL";
|
||||
case OpControlBarrierArriveINTEL: return "OpControlBarrierArriveINTEL";
|
||||
case OpControlBarrierWaitINTEL: return "OpControlBarrierWaitINTEL";
|
||||
case OpArithmeticFenceEXT: return "OpArithmeticFenceEXT";
|
||||
case OpSubgroupBlockPrefetchINTEL: return "OpSubgroupBlockPrefetchINTEL";
|
||||
case OpGroupIMulKHR: return "OpGroupIMulKHR";
|
||||
case OpGroupFMulKHR: return "OpGroupFMulKHR";
|
||||
|
||||
@@ -193,6 +193,7 @@
|
||||
"EarlyAndLateFragmentTestsAMD": 5017,
|
||||
"StencilRefReplacingEXT": 5027,
|
||||
"CoalescingAMDX": 5069,
|
||||
"IsApiEntryAMDX": 5070,
|
||||
"MaxNodeRecursionAMDX": 5071,
|
||||
"StaticNumWorkgroupsAMDX": 5072,
|
||||
"ShaderIndexAMDX": 5073,
|
||||
@@ -205,11 +206,14 @@
|
||||
"StencilRefLessBackAMD": 5084,
|
||||
"QuadDerivativesKHR": 5088,
|
||||
"RequireFullQuadsKHR": 5089,
|
||||
"SharesInputWithAMDX": 5102,
|
||||
"OutputLinesEXT": 5269,
|
||||
"OutputLinesNV": 5269,
|
||||
"OutputPrimitivesEXT": 5270,
|
||||
"OutputPrimitivesNV": 5270,
|
||||
"DerivativeGroupQuadsKHR": 5289,
|
||||
"DerivativeGroupQuadsNV": 5289,
|
||||
"DerivativeGroupLinearKHR": 5290,
|
||||
"DerivativeGroupLinearNV": 5290,
|
||||
"OutputTrianglesEXT": 5298,
|
||||
"OutputTrianglesNV": 5298,
|
||||
@@ -259,7 +263,6 @@
|
||||
"StorageBuffer": 12,
|
||||
"TileImageEXT": 4172,
|
||||
"NodePayloadAMDX": 5068,
|
||||
"NodeOutputPayloadAMDX": 5076,
|
||||
"CallableDataKHR": 5328,
|
||||
"CallableDataNV": 5328,
|
||||
"IncomingCallableDataKHR": 5329,
|
||||
@@ -573,6 +576,10 @@
|
||||
"NodeMaxPayloadsAMDX": 5020,
|
||||
"TrackFinishWritingAMDX": 5078,
|
||||
"PayloadNodeNameAMDX": 5091,
|
||||
"PayloadNodeBaseIndexAMDX": 5098,
|
||||
"PayloadNodeSparseArrayAMDX": 5099,
|
||||
"PayloadNodeArraySizeAMDX": 5100,
|
||||
"PayloadDispatchIndirectAMDX": 5105,
|
||||
"OverrideCoverageNV": 5248,
|
||||
"PassthroughNV": 5250,
|
||||
"ViewportRelativeNV": 5252,
|
||||
@@ -739,7 +746,7 @@
|
||||
"BaryCoordSmoothSampleAMD": 4997,
|
||||
"BaryCoordPullModelAMD": 4998,
|
||||
"FragStencilRefEXT": 5014,
|
||||
"CoalescedInputCountAMDX": 5021,
|
||||
"RemainingRecursionLevelsAMDX": 5021,
|
||||
"ShaderIndexAMDX": 5073,
|
||||
"ViewportMaskNV": 5253,
|
||||
"SecondaryPositionNV": 5257,
|
||||
@@ -852,6 +859,7 @@
|
||||
"DontInline": 1,
|
||||
"Pure": 2,
|
||||
"Const": 3,
|
||||
"OptNoneEXT": 16,
|
||||
"OptNoneINTEL": 16
|
||||
}
|
||||
},
|
||||
@@ -1082,6 +1090,7 @@
|
||||
"MeshShadingEXT": 5283,
|
||||
"FragmentBarycentricKHR": 5284,
|
||||
"FragmentBarycentricNV": 5284,
|
||||
"ComputeDerivativeGroupQuadsKHR": 5288,
|
||||
"ComputeDerivativeGroupQuadsNV": 5288,
|
||||
"FragmentDensityEXT": 5291,
|
||||
"ShadingRateNV": 5291,
|
||||
@@ -1119,6 +1128,7 @@
|
||||
"VulkanMemoryModelDeviceScopeKHR": 5346,
|
||||
"PhysicalStorageBufferAddresses": 5347,
|
||||
"PhysicalStorageBufferAddressesEXT": 5347,
|
||||
"ComputeDerivativeGroupLinearKHR": 5350,
|
||||
"ComputeDerivativeGroupLinearNV": 5350,
|
||||
"RayTracingProvisionalKHR": 5353,
|
||||
"CooperativeMatrixNV": 5357,
|
||||
@@ -1195,11 +1205,13 @@
|
||||
"AtomicFloat32AddEXT": 6033,
|
||||
"AtomicFloat64AddEXT": 6034,
|
||||
"LongCompositesINTEL": 6089,
|
||||
"OptNoneEXT": 6094,
|
||||
"OptNoneINTEL": 6094,
|
||||
"AtomicFloat16AddEXT": 6095,
|
||||
"DebugInfoModuleINTEL": 6114,
|
||||
"BFloat16ConversionINTEL": 6115,
|
||||
"SplitBarrierINTEL": 6141,
|
||||
"ArithmeticFenceEXT": 6144,
|
||||
"FPGAClusterAttributesV2INTEL": 6150,
|
||||
"FPGAKernelAttributesv2INTEL": 6161,
|
||||
"FPMaxErrorINTEL": 6169,
|
||||
@@ -1844,9 +1856,14 @@
|
||||
"OpFragmentMaskFetchAMD": 5011,
|
||||
"OpFragmentFetchAMD": 5012,
|
||||
"OpReadClockKHR": 5056,
|
||||
"OpFinalizeNodePayloadsAMDX": 5075,
|
||||
"OpAllocateNodePayloadsAMDX": 5074,
|
||||
"OpEnqueueNodePayloadsAMDX": 5075,
|
||||
"OpTypeNodePayloadArrayAMDX": 5076,
|
||||
"OpFinishWritingNodePayloadAMDX": 5078,
|
||||
"OpInitializeNodePayloadsAMDX": 5090,
|
||||
"OpNodePayloadArrayLengthAMDX": 5090,
|
||||
"OpIsNodePayloadValidAMDX": 5101,
|
||||
"OpConstantStringAMDX": 5103,
|
||||
"OpSpecConstantStringAMDX": 5104,
|
||||
"OpGroupNonUniformQuadAllKHR": 5110,
|
||||
"OpGroupNonUniformQuadAnyKHR": 5111,
|
||||
"OpHitObjectRecordHitMotionNV": 5249,
|
||||
@@ -2164,6 +2181,7 @@
|
||||
"OpConvertBF16ToFINTEL": 6117,
|
||||
"OpControlBarrierArriveINTEL": 6142,
|
||||
"OpControlBarrierWaitINTEL": 6143,
|
||||
"OpArithmeticFenceEXT": 6145,
|
||||
"OpSubgroupBlockPrefetchINTEL": 6221,
|
||||
"OpGroupIMulKHR": 6401,
|
||||
"OpGroupFMulKHR": 6402,
|
||||
|
||||
Reference in New Issue
Block a user