Add support for RISC-V 64 and LoongArch64 to nvtt (#83)

* nvtt: risc-v 64 and loongarch64

* update

* fix

* fix

* Update debug.h

* update
This commit is contained in:
Glavo
2023-10-08 23:21:54 +08:00
committed by GitHub
parent 82781e44d8
commit 91c22acb22
2 changed files with 23 additions and 1 deletions

View File

@@ -139,6 +139,10 @@
# define NV_CPU_ARM 1 # define NV_CPU_ARM 1
#elif defined POSH_CPU_AARCH64 #elif defined POSH_CPU_AARCH64
# define NV_CPU_AARCH64 1 # define NV_CPU_AARCH64 1
#elif defined POSH_CPU_RISCV64
# define NV_CPU_RISCV64 1
#elif defined POSH_CPU_LOONGARCH64
# define NV_CPU_LOONGARCH64 1
#elif defined POSH_CPU_EMSCRIPTEN #elif defined POSH_CPU_EMSCRIPTEN
# define NV_CPU_EMSCRIPTEN 1 # define NV_CPU_EMSCRIPTEN 1
#else #else
@@ -165,6 +169,14 @@
# define NV_CPU_AARCH64 0 # define NV_CPU_AARCH64 0
#endif // NV_CPU_AARCH64 #endif // NV_CPU_AARCH64
#ifndef NV_CPU_RISCV64
# define NV_CPU_RISCV64 0
#endif // NV_CPU_RISCV64
#ifndef NV_CPU_LOONGARCH64
# define NV_CPU_LOONGARCH64 0
#endif // NV_CPU_LOONGARCH64
#ifndef NV_CPU_EMSCRIPTEN #ifndef NV_CPU_EMSCRIPTEN
# define NV_CPU_EMSCRIPTEN 0 # define NV_CPU_EMSCRIPTEN 0
#endif // NV_CPU_EMSCRIPTEN #endif // NV_CPU_EMSCRIPTEN

View File

@@ -516,6 +516,16 @@ LLVM:
# define POSH_CPU_STRING "IA64" # define POSH_CPU_STRING "IA64"
#endif #endif
#if defined __riscv64 || (defined __riscv && __riscv_xlen == 64)
# define POSH_CPU_RISCV64 1
# define POSH_CPU_STRING "RISC-V 64"
#endif
#if defined __loongarch64 || (defined __loongarch__ && __loongarch_grlen == 64)
# define POSH_CPU_LOONGARCH64 1
# define POSH_CPU_STRING "LoongArch64"
#endif
#if defined __X86__ || defined __i386__ || defined i386 || defined _M_IX86 || defined __386__ || defined __x86_64__ || defined _M_X64 #if defined __X86__ || defined __i386__ || defined i386 || defined _M_IX86 || defined __386__ || defined __x86_64__ || defined _M_X64
# define POSH_CPU_X86 1 # define POSH_CPU_X86 1
# if defined __x86_64__ || defined _M_X64 # if defined __x86_64__ || defined _M_X64
@@ -680,7 +690,7 @@ LLVM:
** the MIPS series, so we have to be careful about those. ** the MIPS series, so we have to be careful about those.
** ---------------------------------------------------------------------------- ** ----------------------------------------------------------------------------
*/ */
#if defined POSH_CPU_X86 || defined POSH_CPU_AXP || defined POSH_CPU_STRONGARM || defined POSH_CPU_AARCH64 || defined POSH_OS_WIN32 || defined POSH_OS_WINCE || defined __MIPSEL__ || defined POSH_CPU_EMSCRIPTEN #if defined POSH_CPU_X86 || defined POSH_CPU_AXP || defined POSH_CPU_STRONGARM || defined POSH_CPU_AARCH64 || defined POSH_CPU_RISCV64 || defined POSH_CPU_LOONGARCH64 || defined POSH_OS_WIN32 || defined POSH_OS_WINCE || defined __MIPSEL__ || defined POSH_CPU_EMSCRIPTEN
# define POSH_ENDIAN_STRING "little" # define POSH_ENDIAN_STRING "little"
# define POSH_LITTLE_ENDIAN 1 # define POSH_LITTLE_ENDIAN 1
#else #else