From 7f1ff198be22de68cd76a4ca175fbb295a0e8e83 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=D0=91=D1=80=D0=B0=D0=BD=D0=B8=D0=BC=D0=B8=D1=80=20=D0=9A?= =?UTF-8?q?=D0=B0=D1=80=D0=B0=D1=9F=D0=B8=D1=9B?= Date: Sun, 14 Sep 2025 09:06:54 -0700 Subject: [PATCH] Updated spirv-headers. --- 3rdparty/spirv-headers/LICENSE | 399 ++++++ .../spirv/unified1/ArmMotionEngine.100.h | 32 + .../include/spirv/unified1/TOSA.001000.1.h | 95 ++ ...extinst.arm.motion-engine.100.grammar.json | 133 ++ .../extinst.opencl.std.100.grammar.json | 348 ++--- .../extinst.tosa.001000.1.grammar.json | 1144 +++++++++++++++++ .../spirv/unified1/spirv.core.grammar.json | 337 ++++- .../include/spirv/unified1/spirv.h | 75 +- .../include/spirv/unified1/spirv.hpp11 | 75 +- .../include/spirv/unified1/spirv.json | 27 + 10 files changed, 2470 insertions(+), 195 deletions(-) create mode 100644 3rdparty/spirv-headers/include/spirv/unified1/ArmMotionEngine.100.h create mode 100644 3rdparty/spirv-headers/include/spirv/unified1/TOSA.001000.1.h create mode 100644 3rdparty/spirv-headers/include/spirv/unified1/extinst.arm.motion-engine.100.grammar.json create mode 100644 3rdparty/spirv-headers/include/spirv/unified1/extinst.tosa.001000.1.grammar.json diff --git a/3rdparty/spirv-headers/LICENSE b/3rdparty/spirv-headers/LICENSE index a02ace17b..a63e9c620 100644 --- a/3rdparty/spirv-headers/LICENSE +++ b/3rdparty/spirv-headers/LICENSE @@ -101,3 +101,402 @@ SOFTWARE. ======================================================================== --- + +Files: **.md, WORKSPACE, .git** + +Attribution 4.0 International + +======================================================================= + +Creative Commons Corporation ("Creative Commons") is not a law firm and +does not provide legal services or legal advice. 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= 2, + ArmMotionEngineInstructionsMax = 0x7fffffff +}; + + +#ifdef __cplusplus +} +#endif + +#endif // SPIRV_UNIFIED1_ArmMotionEngine_100_H_ diff --git a/3rdparty/spirv-headers/include/spirv/unified1/TOSA.001000.1.h b/3rdparty/spirv-headers/include/spirv/unified1/TOSA.001000.1.h new file mode 100644 index 000000000..3da296907 --- /dev/null +++ b/3rdparty/spirv-headers/include/spirv/unified1/TOSA.001000.1.h @@ -0,0 +1,95 @@ +// SPDX-FileCopyrightText: 2022-2025 Arm Ltd. +// SPDX-License-Identifier: MIT + +#ifndef SPIRV_UNIFIED1_TOSA_001000_1_H_ +#define SPIRV_UNIFIED1_TOSA_001000_1_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum { + TOSAVersion = 1000000, + TOSAVersion_BitWidthPadding = 0x7fffffff +}; +enum { + TOSARevision = 1, + TOSARevision_BitWidthPadding = 0x7fffffff +}; + +enum TOSAInstructions { + TOSAARGMAX = 0, + TOSAAVG_POOL2D = 1, + TOSACONV2D = 2, + TOSACONV3D = 3, + TOSADEPTHWISE_CONV2D = 4, + TOSAFFT2D = 5, + TOSAMATMUL = 6, + TOSAMAX_POOL2D = 7, + TOSARFFT2D = 8, + TOSATRANSPOSE_CONV2D = 9, + TOSACLAMP = 10, + TOSAERF = 11, + TOSASIGMOID = 12, + TOSATANH = 13, + TOSAADD = 14, + TOSAARITHMETIC_RIGHT_SHIFT = 15, + TOSABITWISE_AND = 16, + TOSABITWISE_OR = 17, + TOSABITWISE_XOR = 18, + TOSAINTDIV = 19, + TOSALOGICAL_AND = 20, + TOSALOGICAL_LEFT_SHIFT = 21, + TOSALOGICAL_RIGHT_SHIFT = 22, + TOSALOGICAL_OR = 23, + TOSALOGICAL_XOR = 24, + TOSAMAXIMUM = 25, + TOSAMINIMUM = 26, + TOSAMUL = 27, + TOSAPOW = 28, + TOSASUB = 29, + TOSATABLE = 30, + TOSAABS = 31, + TOSABITWISE_NOT = 32, + TOSACEIL = 33, + TOSACLZ = 34, + TOSACOS = 35, + TOSAEXP = 36, + TOSAFLOOR = 37, + TOSALOG = 38, + TOSALOGICAL_NOT = 39, + TOSANEGATE = 40, + TOSARECIPROCAL = 41, + TOSARSQRT = 42, + TOSASIN = 43, + TOSASELECT = 44, + TOSAEQUAL = 45, + TOSAGREATER = 46, + TOSAGREATER_EQUAL = 47, + TOSAREDUCE_ALL = 48, + TOSAREDUCE_ANY = 49, + TOSAREDUCE_MAX = 50, + TOSAREDUCE_MIN = 51, + TOSAREDUCE_PRODUCT = 52, + TOSAREDUCE_SUM = 53, + TOSACONCAT = 54, + TOSAPAD = 55, + TOSARESHAPE = 56, + TOSAREVERSE = 57, + TOSASLICE = 58, + TOSATILE = 59, + TOSATRANSPOSE = 60, + TOSAGATHER = 61, + TOSASCATTER = 62, + TOSARESIZE = 63, + TOSACAST = 64, + TOSARESCALE = 65, + TOSAInstructionsMax = 0x7fffffff +}; + + +#ifdef __cplusplus +} +#endif + +#endif // SPIRV_UNIFIED1_TOSA_001000_1_H_ diff --git a/3rdparty/spirv-headers/include/spirv/unified1/extinst.arm.motion-engine.100.grammar.json b/3rdparty/spirv-headers/include/spirv/unified1/extinst.arm.motion-engine.100.grammar.json new file mode 100644 index 000000000..abcc16e4f --- /dev/null +++ b/3rdparty/spirv-headers/include/spirv/unified1/extinst.arm.motion-engine.100.grammar.json @@ -0,0 +1,133 @@ +{ + "copyright": [ + "SPDX-FileCopyrightText: 2022-2025 Arm Ltd.", + "SPDX-License-Identifier: MIT" + ], + "version": 100, + "revision": 1, + "instructions": [ + { + "opname": "MIN_SAD", + "opcode": 0, + "operands": [ + { + "kind": "IdRef", + "name": "kernel_sizes" + }, + { + "kind": "IdRef", + "name": "search_window_sizes" + }, + { + "kind": "IdRef", + "name": "input_strides" + }, + { + "kind": "IdRef", + "name": "window_strides" + }, + { + "kind": "IdRef", + "name": "window_offsets" + }, + { + "kind": "IdRef", + "name": "padding" + }, + { + "kind": "IdRef", + "name": "search_pattern" + }, + { + "kind": "IdRef", + "name": "input0" + }, + { + "kind": "IdRef", + "name": "input1" + } + ] + }, + { + "opname": "MIN_SAD_COST", + "opcode": 1, + "operands": [ + { + "kind": "IdRef", + "name": "kernel_sizes" + }, + { + "kind": "IdRef", + "name": "search_window_sizes" + }, + { + "kind": "IdRef", + "name": "input_strides" + }, + { + "kind": "IdRef", + "name": "window_strides" + }, + { + "kind": "IdRef", + "name": "window_offsets" + }, + { + "kind": "IdRef", + "name": "padding" + }, + { + "kind": "IdRef", + "name": "search_pattern" + }, + { + "kind": "IdRef", + "name": "input0" + }, + { + "kind": "IdRef", + "name": "input1" + } + ] + }, + { + "opname": "RAW_SAD", + "opcode": 2, + "operands": [ + { + "kind": "IdRef", + "name": "kernel_sizes" + }, + { + "kind": "IdRef", + "name": "search_window_sizes" + }, + { + "kind": "IdRef", + "name": "input_strides" + }, + { + "kind": "IdRef", + "name": "window_strides" + }, + { + "kind": "IdRef", + "name": "window_offsets" + }, + { + "kind": "IdRef", + "name": "padding" + }, + { + "kind": "IdRef", + "name": "input0" + }, + { + "kind": "IdRef", + "name": "input1" + } + ] + } + ], + "operand_kinds": [] +} diff --git a/3rdparty/spirv-headers/include/spirv/unified1/extinst.opencl.std.100.grammar.json b/3rdparty/spirv-headers/include/spirv/unified1/extinst.opencl.std.100.grammar.json index 79394dd87..0b335af28 100644 --- a/3rdparty/spirv-headers/include/spirv/unified1/extinst.opencl.std.100.grammar.json +++ b/3rdparty/spirv-headers/include/spirv/unified1/extinst.opencl.std.100.grammar.json @@ -708,6 +708,130 @@ { "kind" : "IdRef", "name" : "x" } ] }, + { + "opname" : "fclamp", + "opcode" : 95, + "operands" : [ + { "kind" : "IdRef", "name" : "x" }, + { "kind" : "IdRef", "name" : "minval" }, + { "kind" : "IdRef", "name" : "maxval" } + ] + }, + { + "opname" : "degrees", + "opcode" :96, + "operands" : [ + { "kind" : "IdRef", "name" : "radians" } + ] + }, + { + "opname" : "fmax_common", + "opcode" : 97, + "operands" : [ + { "kind" : "IdRef", "name" : "x" }, + { "kind" : "IdRef", "name" : "y" } + ] + }, + { + "opname" : "fmin_common", + "opcode" : 98, + "operands" : [ + { "kind" : "IdRef", "name" : "x" }, + { "kind" : "IdRef", "name" : "y" } + ] + }, + { + "opname" : "mix", + "opcode" : 99, + "operands" : [ + { "kind" : "IdRef", "name" : "x" }, + { "kind" : "IdRef", "name" : "y" }, + { "kind" : "IdRef", "name" : "a" } + ] + }, + { + "opname" : "radians", + "opcode" : 100, + "operands" : [ + { "kind" : "IdRef", "name" : "degrees" } + ] + }, + { + "opname" : "step", + "opcode" : 101, + "operands" : [ + { "kind" : "IdRef", "name" : "edge" }, + { "kind" : "IdRef", "name" : "x" } + ] + }, + { + "opname" : "smoothstep", + "opcode" : 102, + "operands" : [ + { "kind" : "IdRef", "name" : "edge0" }, + { "kind" : "IdRef", "name" : "edge1" }, + { "kind" : "IdRef", "name" : "x" } + ] + }, + { + "opname" : "sign", + "opcode" : 103, + "operands" : [ + { "kind" : "IdRef", "name" : "x" } + ] + }, + { + "opname" : "cross", + "opcode" : 104, + "operands" : [ + { "kind" : "IdRef", "name" : "p0" }, + { "kind" : "IdRef", "name" : "p1" } + ] + }, + { + "opname" : "distance", + "opcode" : 105, + "operands" : [ + { "kind" : "IdRef", "name" : "p0" }, + { "kind" : "IdRef", "name" : "p1" } + ] + }, + { + "opname" : "length", + "opcode" : 106, + "operands" : [ + { "kind" : "IdRef", "name" : "p" } + ] + }, + { + "opname" : "normalize", + "opcode" : 107, + "operands" : [ + { "kind" : "IdRef", "name" : "p" } + ] + }, + { + "opname" : "fast_distance", + "opcode" : 108, + "operands" : [ + { "kind" : "IdRef", "name" : "p0" }, + { "kind" : "IdRef", "name" : "p1" } + ] + }, + { + "opname" : "fast_length", + "opcode" : 109, + "operands" : [ + { "kind" : "IdRef", "name" : "p" } + ] + }, + { + "opname" : "fast_normalize", + "opcode" : 110, + "operands" : [ + { "kind" : "IdRef", "name" : "p" } + ] + }, { "opname" : "s_abs", "opcode" : 141, @@ -951,180 +1075,6 @@ { "kind" : "IdRef", "name" : "y" } ] }, - { - "opname" : "u_abs", - "opcode" : 201, - "operands" : [ - { "kind" : "IdRef", "name" : "x" } - ] - }, - { - "opname" : "u_abs_diff", - "opcode" : 202, - "operands" : [ - { "kind" : "IdRef", "name" : "x" }, - { "kind" : "IdRef", "name" : "y" } - ] - }, - { - "opname" : "u_mul_hi", - "opcode" : 203, - "operands" : [ - { "kind" : "IdRef", "name" : "x" }, - { "kind" : "IdRef", "name" : "y" } - ] - }, - { - "opname" : "u_mad_hi", - "opcode" : 204, - "operands" : [ - { "kind" : "IdRef", "name" : "a" }, - { "kind" : "IdRef", "name" : "b" }, - { "kind" : "IdRef", "name" : "c" } - ] - }, - { - "opname" : "fclamp", - "opcode" : 95, - "operands" : [ - { "kind" : "IdRef", "name" : "x" }, - { "kind" : "IdRef", "name" : "minval" }, - { "kind" : "IdRef", "name" : "maxval" } - ] - }, - { - "opname" : "degrees", - "opcode" :96, - "operands" : [ - { "kind" : "IdRef", "name" : "radians" } - ] - }, - { - "opname" : "fmax_common", - "opcode" : 97, - "operands" : [ - { "kind" : "IdRef", "name" : "x" }, - { "kind" : "IdRef", "name" : "y" } - ] - }, - { - "opname" : "fmin_common", - "opcode" : 98, - "operands" : [ - { "kind" : "IdRef", "name" : "x" }, - { "kind" : "IdRef", "name" : "y" } - ] - }, - { - "opname" : "mix", - "opcode" : 99, - "operands" : [ - { "kind" : "IdRef", "name" : "x" }, - { "kind" : "IdRef", "name" : "y" }, - { "kind" : "IdRef", "name" : "a" } - ] - }, - { - "opname" : "radians", - "opcode" : 100, - "operands" : [ - { "kind" : "IdRef", "name" : "degrees" } - ] - }, - { - "opname" : "step", - "opcode" : 101, - "operands" : [ - { "kind" : "IdRef", "name" : "edge" }, - { "kind" : "IdRef", "name" : "x" } - ] - }, - { - "opname" : "smoothstep", - "opcode" : 102, - "operands" : [ - { "kind" : "IdRef", "name" : "edge0" }, - { "kind" : "IdRef", "name" : "edge1" }, - { "kind" : "IdRef", "name" : "x" } - ] - }, - { - "opname" : "sign", - "opcode" : 103, - "operands" : [ - { "kind" : "IdRef", "name" : "x" } - ] - }, - { - "opname" : "cross", - "opcode" : 104, - "operands" : [ - { "kind" : "IdRef", "name" : "p0" }, - { "kind" : "IdRef", "name" : "p1" } - ] - }, - { - "opname" : "distance", - "opcode" : 105, - "operands" : [ - { "kind" : "IdRef", "name" : "p0" }, - { "kind" : "IdRef", "name" : "p1" } - ] - }, - { - "opname" : "length", - "opcode" : 106, - "operands" : [ - { "kind" : "IdRef", "name" : "p" } - ] - }, - { - "opname" : "normalize", - "opcode" : 107, - "operands" : [ - { "kind" : "IdRef", "name" : "p" } - ] - }, - { - "opname" : "fast_distance", - "opcode" : 108, - "operands" : [ - { "kind" : "IdRef", "name" : "p0" }, - { "kind" : "IdRef", "name" : "p1" } - ] - }, - { - "opname" : "fast_length", - "opcode" : 109, - "operands" : [ - { "kind" : "IdRef", "name" : "p" } - ] - }, - { - "opname" : "fast_normalize", - "opcode" : 110, - "operands" : [ - { "kind" : "IdRef", "name" : "p" } - ] - }, - { - "opname" : "bitselect", - "opcode" : 186, - "operands" : [ - { "kind" : "IdRef", "name" : "a" }, - { "kind" : "IdRef", "name" : "b" }, - { "kind" : "IdRef", "name" : "c" } - ] - }, - { - "opname" : "select", - "opcode" : 187, - "operands" : [ - { "kind" : "IdRef", "name" : "a" }, - { "kind" : "IdRef", "name" : "b" }, - { "kind" : "IdRef", "name" : "c" } - ] - }, { "opname" : "vloadn", "opcode" : 171, @@ -1258,6 +1208,56 @@ { "kind" : "IdRef", "name" : "ptr" }, { "kind" : "IdRef", "name" : "num elements" } ] + }, + { + "opname" : "bitselect", + "opcode" : 186, + "operands" : [ + { "kind" : "IdRef", "name" : "a" }, + { "kind" : "IdRef", "name" : "b" }, + { "kind" : "IdRef", "name" : "c" } + ] + }, + { + "opname" : "select", + "opcode" : 187, + "operands" : [ + { "kind" : "IdRef", "name" : "a" }, + { "kind" : "IdRef", "name" : "b" }, + { "kind" : "IdRef", "name" : "c" } + ] + }, + { + "opname" : "u_abs", + "opcode" : 201, + "operands" : [ + { "kind" : "IdRef", "name" : "x" } + ] + }, + { + "opname" : "u_abs_diff", + "opcode" : 202, + "operands" : [ + { "kind" : "IdRef", "name" : "x" }, + { "kind" : "IdRef", "name" : "y" } + ] + }, + { + "opname" : "u_mul_hi", + "opcode" : 203, + "operands" : [ + { "kind" : "IdRef", "name" : "x" }, + { "kind" : "IdRef", "name" : "y" } + ] + }, + { + "opname" : "u_mad_hi", + "opcode" : 204, + "operands" : [ + { "kind" : "IdRef", "name" : "a" }, + { "kind" : "IdRef", "name" : "b" }, + { "kind" : "IdRef", "name" : "c" } + ] } ] } diff --git a/3rdparty/spirv-headers/include/spirv/unified1/extinst.tosa.001000.1.grammar.json b/3rdparty/spirv-headers/include/spirv/unified1/extinst.tosa.001000.1.grammar.json new file mode 100644 index 000000000..cabab82fb --- /dev/null +++ b/3rdparty/spirv-headers/include/spirv/unified1/extinst.tosa.001000.1.grammar.json @@ -0,0 +1,1144 @@ +{ + "copyright": [ + "SPDX-FileCopyrightText: 2022-2025 Arm Ltd.", + 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{ + "kind": "IdRef", + "name": "input1" + }, + { + "kind": "IdRef", + "name": "input2" + }, + { + "kind": "IdRef", + "name": "input3" + } + ] + }, + { + "opname": "EQUAL", + "opcode": 45, + "operands": [ + { + "kind": "IdRef", + "name": "input1" + }, + { + "kind": "IdRef", + "name": "input2" + } + ] + }, + { + "opname": "GREATER", + "opcode": 46, + "operands": [ + { + "kind": "IdRef", + "name": "input1" + }, + { + "kind": "IdRef", + "name": "input2" + } + ] + }, + { + "opname": "GREATER_EQUAL", + "opcode": 47, + "operands": [ + { + "kind": "IdRef", + "name": "input1" + }, + { + "kind": "IdRef", + "name": "input2" + } + ] + }, + { + "opname": "REDUCE_ALL", + "opcode": 48, + "operands": [ + { + "kind": "IdRef", + "name": "axis" + }, + { + "kind": "IdRef", + "name": "input" + } + ] + }, + { + "opname": "REDUCE_ANY", + "opcode": 49, + "operands": [ + { + "kind": "IdRef", + "name": "axis" + }, + { + "kind": "IdRef", + "name": "input" + } + ] + }, + { + "opname": "REDUCE_MAX", + "opcode": 50, + "operands": [ + { + "kind": "IdRef", + "name": "axis" + }, + { + "kind": "IdRef", + "name": "nan_mode" + }, + { + "kind": "IdRef", + "name": "input" + } + ] + }, + { + "opname": "REDUCE_MIN", + "opcode": 51, + "operands": [ + { + "kind": "IdRef", + "name": "axis" + }, + { + "kind": "IdRef", + "name": "nan_mode" + }, + { + "kind": "IdRef", + "name": "input" + } + ] + }, + { + "opname": "REDUCE_PRODUCT", + "opcode": 52, + "operands": [ + { + "kind": "IdRef", + "name": "axis" + }, + { + "kind": "IdRef", + "name": "input" + } + ] + }, + { + "opname": "REDUCE_SUM", + "opcode": 53, + "operands": [ + { + "kind": "IdRef", + "name": "axis" + }, + { + "kind": "IdRef", + "name": "input" + } + ] + }, + { + "opname": "CONCAT", + "opcode": 54, + "operands": [ + { + "kind": "IdRef", + "name": "axis" + }, + { + "kind": "IdRef", + "name": "input1", + "quantifier": "*" + } + ] + }, + { + "opname": "PAD", + "opcode": 55, + "operands": [ + { + "kind": "IdRef", + "name": "input1" + }, + { + "kind": "IdRef", + "name": "padding" + }, + { + "kind": "IdRef", + "name": "pad_const" + } + ] + }, + { + "opname": "RESHAPE", + "opcode": 56, + "operands": [ + { + "kind": "IdRef", + "name": "input1" + }, + { + "kind": "IdRef", + "name": "shape" + } + ] + }, + { + "opname": "REVERSE", + "opcode": 57, + "operands": [ + { + "kind": "IdRef", + "name": "axis" + }, + { + "kind": "IdRef", + "name": "input1" + } + ] + }, + { + "opname": "SLICE", + "opcode": 58, + "operands": [ + { + "kind": "IdRef", + "name": "input1" + }, + { + "kind": "IdRef", + "name": "start" + }, + { + "kind": "IdRef", + "name": "size" + } + ] + }, + { + "opname": "TILE", + "opcode": 59, + "operands": [ + { + "kind": "IdRef", + "name": "input1" + }, + { + "kind": "IdRef", + "name": "multiples" + } + ] + }, + { + "opname": "TRANSPOSE", + "opcode": 60, + "operands": [ + { + "kind": "IdRef", + "name": "perms" + }, + { + "kind": "IdRef", + "name": "input1" + } + ] + }, + { + "opname": "GATHER", + "opcode": 61, + "operands": [ + { + "kind": "IdRef", + "name": "values" + }, + { + "kind": "IdRef", + "name": "indices" + } + ] + }, + { + "opname": "SCATTER", + "opcode": 62, + "operands": [ + { + "kind": "IdRef", + "name": "values_in" + }, + { + "kind": "IdRef", + "name": "indices" + }, + { + "kind": "IdRef", + "name": "input" + } + ] + }, + { + "opname": "RESIZE", + "opcode": 63, + "operands": [ + { + "kind": "IdRef", + "name": "mode" + }, + { + "kind": "IdRef", + "name": "input" + }, + { + "kind": "IdRef", + "name": "scale" + }, + { + "kind": "IdRef", + "name": "offset" + }, + { + "kind": "IdRef", + "name": "border" + } + ] + }, + { + "opname": "CAST", + "opcode": 64, + "operands": [ + { + "kind": "IdRef", + "name": "input" + } + ] + }, + { + "opname": "RESCALE", + "opcode": 65, + "operands": [ + { + "kind": "IdRef", + "name": "scale32" + }, + { + "kind": "IdRef", + "name": "rounding_mode" + }, + { + "kind": "IdRef", + "name": "per_channel" + }, + { + "kind": "IdRef", + "name": "input_unsigned" + }, + { + "kind": "IdRef", + "name": "output_unsigned" + }, + { + "kind": "IdRef", + "name": "input" + }, + { + "kind": "IdRef", + "name": "multiplier" + }, + { + "kind": "IdRef", + "name": "shift" + }, + { + "kind": "IdRef", + "name": "input_zp" + }, + { + "kind": "IdRef", + "name": "output_zp" + } + ] + } + ], + "operand_kinds": [] +} diff --git a/3rdparty/spirv-headers/include/spirv/unified1/spirv.core.grammar.json b/3rdparty/spirv-headers/include/spirv/unified1/spirv.core.grammar.json index b7df252f0..eb247f72a 100644 --- a/3rdparty/spirv-headers/include/spirv/unified1/spirv.core.grammar.json +++ b/3rdparty/spirv-headers/include/spirv/unified1/spirv.core.grammar.json @@ -116,6 +116,10 @@ "tag" : "Tensor", "heading" : "Tensor Instructions" }, + { + "tag" : "Graph", + "heading" : "Graph Instructions" + }, { "tag" : "Reserved", "heading" : "Reserved Instructions" @@ -1355,6 +1359,7 @@ { "kind" : "IdResult" }, { "kind" : "IdRef", "name" : "Value" } ], + "capabilities" : [ "Shader" ], "version": "1.0" }, { @@ -3914,7 +3919,7 @@ { "kind" : "IdResult" }, { "kind" : "IdScope", "name" : "Execution" }, { "kind" : "IdRef", "name" : "Value" }, - { "kind" : "IdRef", "name" : "Id" } + { "kind" : "IdRef", "name" : "Invocation Id" } ], "capabilities" : [ "GroupNonUniformBallot" ], "version" : "1.3" @@ -4021,7 +4026,7 @@ { "kind" : "IdResult" }, { "kind" : "IdScope", "name" : "Execution" }, { "kind" : "IdRef", "name" : "Value" }, - { "kind" : "IdRef", "name" : "Id" } + { "kind" : "IdRef", "name" : "Invocation Id" } ], "capabilities" : [ "GroupNonUniformShuffle" ], "version" : "1.3" @@ -4474,6 +4479,85 @@ "capabilities" : [ "TensorsARM" ], "version" : "None" }, + { + "opname" : "OpGraphConstantARM", + "class" : "Graph", + "opcode" : 4181, + "operands" : [ + { "kind" : "IdResultType" }, + { "kind" : "IdResult" }, + { "kind" : "LiteralInteger", "name" : "GraphConstantID" } + ], + "capabilities" : [ "GraphARM" ], + "version" : "None" + }, + { + "opname" : "OpGraphEntryPointARM", + "class" : "Graph", + "opcode" : 4182, + "operands" : [ + { "kind" : "IdRef", "name" : "Graph" }, + { "kind" : "LiteralString", "name" : "Name" }, + { "kind" : "IdRef", "quantifier" : "*", "name" : "Interface" } + ], + "capabilities" : [ "GraphARM" ], + "version" : "None" + }, + { + "opname" : "OpGraphARM", + "class" : "Graph", + "opcode" : 4183, + "operands" : [ + { "kind" : "IdResultType" }, + { "kind" : "IdResult" } + ], + "capabilities" : [ "GraphARM" ], + "version" : "None" + }, + { + "opname" : "OpGraphInputARM", + "class" : "Graph", + "opcode" : 4184, + "operands" : [ + { "kind" : "IdResultType" }, + { "kind" : "IdResult" }, + { "kind" : "IdRef", "name" : "InputIndex" }, + { "kind" : "IdRef", "quantifier" : "*", "name" : "ElementIndex" } + ], + "capabilities" : [ "GraphARM" ], + "version" : "None" + }, + { + "opname" : "OpGraphSetOutputARM", + "class" : "Graph", + "opcode" : 4185, + "operands" : [ + { "kind" : "IdRef", "name": "Value" }, + { "kind" : "IdRef", "name" : "OutputIndex" }, + { "kind" : "IdRef", "quantifier" : "*", "name" : "ElementIndex" } + ], + "capabilities" : [ "GraphARM" ], + "version" : "None" + }, + { + "opname" : "OpGraphEndARM", + "class" : "Graph", + "opcode" : 4186, + "capabilities" : [ "GraphARM" ], + "version" : "None" + }, + { + "opname" : "OpTypeGraphARM", + "class" : "Type-Declaration", + "opcode" : 4190, + "operands" : [ + { "kind" : "IdResult" }, + { "kind" : "LiteralInteger", "name" : "NumInputs" }, + { "kind" : "IdRef", "quantifier" : "*", "name" : "InOutTypes" } + ], + "capabilities" : [ "GraphARM" ], + "version" : "None" + }, { "opname" : "OpTerminateInvocation", "class" : "Control-Flow", @@ -4491,7 +4575,6 @@ "capabilities" : [ "UntypedPointersKHR" ], - "provisional" : true, "version" : "None", "operands" : [ { "kind" : "IdResult" }, @@ -4503,7 +4586,6 @@ "class" : "Memory", "opcode" : 4418, "capabilities" : [ "UntypedPointersKHR" ], - "provisional" : true, "version" : "None", "operands" : [ { "kind" : "IdResultType" }, @@ -4518,7 +4600,6 @@ "class" : "Memory", "opcode" : 4419, "capabilities" : [ "UntypedPointersKHR" ], - "provisional" : true, "version" : "None", "operands" : [ { "kind" : "IdResultType" }, @@ -4533,7 +4614,6 @@ "class" : "Memory", "opcode" : 4420, "capabilities" : [ "UntypedPointersKHR" ], - "provisional" : true, "version" : "None", "operands" : [ { "kind" : "IdResultType" }, @@ -4574,7 +4654,6 @@ "class" : "Memory", "opcode" : 4423, "capabilities" : [ "UntypedPointersKHR" ], - "provisional" : true, "version" : "None", "operands" : [ { "kind" : "IdResultType" }, @@ -4590,7 +4669,6 @@ "class" : "Memory", "opcode" : 4424, "capabilities" : [ "UntypedPointersKHR" ], - "provisional" : true, "version" : "None", "operands" : [ { "kind" : "IdResultType" }, @@ -4606,7 +4684,6 @@ "class" : "Memory", "opcode" : 4425, "capabilities" : [ "UntypedPointersKHR" ], - "provisional" : true, "version" : "None", "operands" : [ { "kind" : "IdResultType" }, @@ -4621,7 +4698,6 @@ "class" : "Memory", "opcode" : 4426, "capabilities" : [ "UntypedPointersKHR" ], - "provisional" : true, "version" : "None", "operands" : [ { "kind" : "IdRef", "name" : "Pointer Type" }, @@ -4719,6 +4795,26 @@ "extensions" : [ "SPV_KHR_relaxed_extended_instruction" ], "version": "None" }, + { + "opname" : "OpUntypedGroupAsyncCopyKHR", + "class" : "Group", + "opcode" : 4434, + "capabilities" : [ "UntypedPointersKHR" ], + "version" : "None", + "operands" : [ + { "kind" : "IdResultType" }, + { "kind" : "IdResult" }, + { "kind" : "IdRef", "name" : "Execution" }, + { "kind" : "IdRef", "name" : "Destination" }, + { "kind" : "IdRef", "name" : "Source" }, + { "kind" : "IdRef", "name" : "Element Num Bytes" }, + { "kind" : "IdRef", "name" : "Num Elements" }, + { "kind" : "IdRef", "name" : "Stride" }, + { "kind" : "IdRef", "name" : "Event" }, + { "kind" : "MemoryAccess", "quantifier" : "?", "name" : "Destination Memory Operands" }, + { "kind" : "MemoryAccess", "quantifier" : "?", "name" : "Source Memory Operands" } + ] + }, { "opname" : "OpTraceRayKHR", "class" : "Reserved", @@ -5185,6 +5281,18 @@ "capabilities" : [ "TextureBlockMatchQCOM" ], "version" : "None" }, + { + "opname" : "OpBitCastArrayQCOM", + "class" : "Conversion", + "opcode" : 4497, + "operands" : [ + { "kind" : "IdResultType" }, + { "kind" : "IdResult" }, + { "kind" : "IdRef", "name" : "Source Array" } + ], + "capabilities" : [ "CooperativeMatrixConversionQCOM" ], + "version" : "None" + }, { "opname" : "OpImageBlockMatchWindowSSDQCOM", "class" : "Image", @@ -5249,6 +5357,43 @@ "capabilities" : [ "TextureBlockMatch2QCOM" ], "version" : "None" }, + { + "opname" : "OpCompositeConstructCoopMatQCOM", + "class" : "Composite", + "opcode" : 4540, + "operands" : [ + { "kind" : "IdResultType" }, + { "kind" : "IdResult" }, + { "kind" : "IdRef", "name" : "Source Array" } + ], + "capabilities" : [ "CooperativeMatrixConversionQCOM" ], + "version" : "None" + }, + { + "opname" : "OpCompositeExtractCoopMatQCOM", + "class" : "Composite", + "opcode" : 4541, + "operands" : [ + { "kind" : "IdResultType" }, + { "kind" : "IdResult" }, + { "kind" : "IdRef", "name" : "Source Cooperative Matrix" } + ], + "capabilities" : [ "CooperativeMatrixConversionQCOM" ], + "version" : "None" + }, + { + "opname" : "OpExtractSubArrayQCOM", + "class" : "Composite", + "opcode" : 4542, + "operands" : [ + { "kind" : "IdResultType" }, + { "kind" : "IdResult" }, + { "kind" : "IdRef", "name" : "Source Array" }, + { "kind" : "IdRef", "name" : "index" } + ], + "capabilities" : [ "CooperativeMatrixConversionQCOM" ], + "version" : "None" + }, { "opname" : "OpGroupIAddNonUniformAMD", "class" : "Group", @@ -6359,8 +6504,9 @@ "version" : "None" }, { - "opname" : "OpRayQueryGetClusterIdNV", + "opname" : "OpRayQueryGetIntersectionClusterIdNV", "class" : "Reserved", + "aliases" : ["OpRayQueryGetClusterIdNV"], "opcode" : 5345, "operands" : [ { "kind" : "IdResultType" }, @@ -8093,7 +8239,7 @@ { "kind" : "IdResult" }, { "kind" : "IdRef", "name" : "Fwd Ref Offset" }, { "kind" : "IdRef", "name" : "Bwd Ref Offset" }, - { "kind" : "IdRef", "name" : "id> Search Window Config" }, + { "kind" : "IdRef", "name" : "Search Window Config" }, { "kind" : "IdRef", "name" : "Payload" } ], "capabilities" : [ "SubgroupAvcMotionEstimationINTEL" ], @@ -9010,19 +9156,19 @@ }, { "opname" : "OpVariableLengthArrayINTEL", - "class" : "@exclude", + "class" : "Memory", "opcode" : 5818, "operands" : [ { "kind" : "IdResultType" }, { "kind" : "IdResult" }, - { "kind" : "IdRef", "name" : "Lenght" } + { "kind" : "IdRef", "name" : "Length" } ], "capabilities" : [ "VariableLengthArrayINTEL" ], "version" : "None" }, { "opname" : "OpSaveMemoryINTEL", - "class" : "@exclude", + "class" : "Memory", "opcode" : 5819, "operands" : [ { "kind" : "IdResultType" }, @@ -9033,7 +9179,7 @@ }, { "opname" : "OpRestoreMemoryINTEL", - "class" : "@exclude", + "class" : "Memory", "opcode" : 5820, "operands" : [ { "kind" : "IdRef", "name" : "Ptr" } @@ -10694,6 +10840,114 @@ "capabilities" : [ "TernaryBitwiseFunctionINTEL" ], "version" : "None" }, + { + "opname" : "OpUntypedVariableLengthArrayINTEL", + "class" : "Memory", + "opcode" : 6244, + "operands" : [ + { "kind" : "IdResultType" }, + { "kind" : "IdResult" }, + { "kind" : "IdRef", "name" : "Element Type" }, + { "kind" : "IdRef", "name" : "Length" } + ], + "capabilities" : [ "UntypedVariableLengthArrayINTEL" ], + "version" : "None" + }, + { + "opname" : "OpConditionalExtensionINTEL", + "class" : "Extension", + "opcode" : 6248, + "operands" : [ + { "kind" : "IdRef", "name" : "Condition" }, + { "kind" : "LiteralString", "name" : "Name" } + ], + "capabilities" : [ "SpecConditionalINTEL" ], + "provisional" : true, + "version" : "None" + }, + { + "opname" : "OpConditionalEntryPointINTEL", + "class" : "Mode-Setting", + "opcode" : 6249, + "operands" : [ + { "kind" : "IdRef", "name" : "Condition" }, + { "kind" : "ExecutionModel" }, + { "kind" : "IdRef", "name" : "Entry Point" }, + { "kind" : "LiteralString", "name" : "Name" }, + { "kind" : "IdRef", "quantifier" : "*", "name" : "Interface" } + ], + "capabilities" : [ "SpecConditionalINTEL" ], + "provisional" : true, + "version" : "None" + }, + { + "opname" : "OpConditionalCapabilityINTEL", + "class" : "Mode-Setting", + "opcode" : 6250, + "operands" : [ + { "kind" : "IdRef", "name" : "Condition" }, + { "kind" : "Capability", "name" : "Capability" } + ], + "capabilities" : [ "SpecConditionalINTEL" ], + "provisional" : true, + "version" : "None" + }, + { + "opname" : "OpSpecConstantTargetINTEL", + "class" : "Constant-Creation", + "opcode" : 6251, + "operands" : [ + { "kind" : "IdResultType" }, + { "kind" : "IdResult" }, + { "kind" : "LiteralInteger", "name" : "Target" }, + { "kind" : "LiteralInteger", "quantifier" : "*", "name" : "Features" } + ], + "capabilities" : [ "FunctionVariantsINTEL" ], + "provisional" : true, + "version": "None" + }, + { + "opname" : "OpSpecConstantArchitectureINTEL", + "class" : "Constant-Creation", + "opcode" : 6252, + "operands" : [ + { "kind" : "IdResultType" }, + { "kind" : "IdResult" }, + { "kind" : "LiteralInteger", "name" : "Category" }, + { "kind" : "LiteralInteger", "name" : "Family" }, + { "kind" : "LiteralInteger", "name" : "Opcode" }, + { "kind" : "LiteralInteger", "name" : "Architecture" } + ], + "capabilities" : [ "FunctionVariantsINTEL" ], + "provisional" : true, + "version": "None" + }, + { + "opname" : "OpSpecConstantCapabilitiesINTEL", + "class" : "Constant-Creation", + "opcode" : 6253, + "operands" : [ + { "kind" : "IdResultType" }, + { "kind" : "IdResult" }, + { "kind" : "Capability", "quantifier" : "*", "name" : "Capabilities" } + ], + "capabilities" : [ "FunctionVariantsINTEL" ], + "provisional" : true, + "version": "None" + }, + { + "opname" : "OpConditionalCopyObjectINTEL", + "class" : "Composite", + "opcode" : 6254, + "operands" : [ + { "kind" : "IdResultType" }, + { "kind" : "IdResult" }, + { "kind" : "IdRef", "quantifier" : "*", "name" : "Condition 0, Operand 0, +\nCondition 1, Operand 1, +\n..." } + ], + "capabilities" : [ "SpecConditionalINTEL" ], + "provisional" : true, + "version" : "None" + }, { "opname" : "OpGroupIMulKHR", "class" : "Group", @@ -12408,7 +12662,7 @@ "enumerant" : "DerivativeGroupQuadsKHR", "aliases" : ["DerivativeGroupQuadsNV"], "value" : 5289, - "capabilities" : [ "ComputeDerivativeGroupQuadsNV", "ComputeDerivativeGroupQuadsKHR" ], + "capabilities" : [ "ComputeDerivativeGroupQuadsKHR" ], "extensions" : [ "SPV_NV_compute_shader_derivatives", "SPV_KHR_compute_shader_derivatives" ], "version" : "None" }, @@ -12416,7 +12670,7 @@ "enumerant" : "DerivativeGroupLinearKHR", "aliases" : ["DerivativeGroupLinearNV"], "value" : 5290, - "capabilities" : [ "ComputeDerivativeGroupLinearNV", "ComputeDerivativeGroupLinearKHR" ], + "capabilities" : [ "ComputeDerivativeGroupLinearKHR" ], "extensions" : [ "SPV_NV_compute_shader_derivatives", "SPV_KHR_compute_shader_derivatives" ], "version" : "None" }, @@ -14817,6 +15071,16 @@ "capabilities" : [ "GlobalVariableFPGADecorationsINTEL" ], "version" : "None" }, + { + "enumerant" : "ConditionalINTEL", + "value" : 6247, + "parameters": [ + { "kind" : "IdRef", "name" : "Condition" } + ], + "capabilities" : [ "SpecConditionalINTEL" ], + "provisional" : true, + "version" : "None" + }, { "enumerant" : "CacheControlLoadINTEL", "value" : 6442, @@ -16252,6 +16516,12 @@ "extensions" : [ "SPV_ARM_tensors"], "version" : "None" }, + { + "enumerant" : "GraphARM", + "value" : 4191, + "extensions" : [ "SPV_ARM_graph"], + "version" : "None" + }, { "enumerant" : "CooperativeMatrixLayoutsARM", "value" : 4201, @@ -16267,6 +16537,7 @@ { "enumerant" : "Float8CooperativeMatrixEXT", "value" : 4213, + "capabilities" : [ "Float8EXT", "CooperativeMatrixKHR" ], "extensions" : [ "SPV_EXT_float8"], "version" : "None" }, @@ -16451,7 +16722,6 @@ "enumerant" : "UntypedPointersKHR", "value" : 4473, "extensions" : [ "SPV_KHR_untyped_pointers" ], - "provisional" : true, "version" : "None" }, { @@ -16493,6 +16763,13 @@ "extensions" : [ "SPV_QCOM_tile_shading" ], "version" : "None" }, + { + "enumerant" : "CooperativeMatrixConversionQCOM", + "value" : 4496, + "capabilities" : [ "CooperativeMatrixKHR" ], + "extensions" : [ "SPV_QCOM_cooperative_matrix_conversion" ], + "version" : "None" + }, { "enumerant" : "TextureBlockMatch2QCOM", "value" : 4498, @@ -17473,6 +17750,28 @@ "extensions" : [ "SPV_INTEL_ternary_bitwise_function"], "version" : "None" }, + { + "enumerant" : "UntypedVariableLengthArrayINTEL", + "value" : 6243, + "capabilities" : [ "VariableLengthArrayINTEL", "UntypedPointersKHR" ], + "extensions" : [ "SPV_INTEL_variable_length_array" ], + "version" : "None" + }, + { + "enumerant" : "SpecConditionalINTEL", + "value" : 6245, + "extensions" : [ "SPV_INTEL_function_variants" ], + "provisional" : true, + "version": "None" + }, + { + "enumerant" : "FunctionVariantsINTEL", + "value" : 6246, + "capabilities" : [ "SpecConditionalINTEL" ], + "extensions" : [ "SPV_INTEL_function_variants" ], + "provisional" : true, + "version": "None" + }, { "enumerant" : "GroupUniformArithmeticKHR", "value" : 6400, diff --git a/3rdparty/spirv-headers/include/spirv/unified1/spirv.h b/3rdparty/spirv-headers/include/spirv/unified1/spirv.h index 4128040b6..12d0bf9d9 100644 --- a/3rdparty/spirv-headers/include/spirv/unified1/spirv.h +++ b/3rdparty/spirv-headers/include/spirv/unified1/spirv.h @@ -642,6 +642,7 @@ typedef enum SpvDecoration_ { SpvDecorationHostAccessINTEL = 6188, SpvDecorationInitModeINTEL = 6190, SpvDecorationImplementInRegisterMapINTEL = 6191, + SpvDecorationConditionalINTEL = 6247, SpvDecorationCacheControlLoadINTEL = 6442, SpvDecorationCacheControlStoreINTEL = 6443, SpvDecorationMax = 0x7fffffff, @@ -1067,6 +1068,7 @@ typedef enum SpvCapability_ { SpvCapabilityTensorsARM = 4174, SpvCapabilityStorageTensorArrayDynamicIndexingARM = 4175, SpvCapabilityStorageTensorArrayNonUniformIndexingARM = 4176, + SpvCapabilityGraphARM = 4191, SpvCapabilityCooperativeMatrixLayoutsARM = 4201, SpvCapabilityFloat8EXT = 4212, SpvCapabilityFloat8CooperativeMatrixEXT = 4213, @@ -1106,6 +1108,7 @@ typedef enum SpvCapability_ { SpvCapabilityTextureBoxFilterQCOM = 4485, SpvCapabilityTextureBlockMatchQCOM = 4486, SpvCapabilityTileShadingQCOM = 4495, + SpvCapabilityCooperativeMatrixConversionQCOM = 4496, SpvCapabilityTextureBlockMatch2QCOM = 4498, SpvCapabilityFloat16ImageAMD = 5008, SpvCapabilityImageGatherBiasLodAMD = 5009, @@ -1281,6 +1284,9 @@ typedef enum SpvCapability_ { SpvCapabilitySubgroup2DBlockTransposeINTEL = 6230, SpvCapabilitySubgroupMatrixMultiplyAccumulateINTEL = 6236, SpvCapabilityTernaryBitwiseFunctionINTEL = 6241, + SpvCapabilityUntypedVariableLengthArrayINTEL = 6243, + SpvCapabilitySpecConditionalINTEL = 6245, + SpvCapabilityFunctionVariantsINTEL = 6246, SpvCapabilityGroupUniformArithmeticKHR = 6400, SpvCapabilityTensorFloat32RoundingINTEL = 6425, SpvCapabilityMaskedGatherScatterINTEL = 6427, @@ -1951,6 +1957,13 @@ typedef enum SpvOp_ { SpvOpTensorReadARM = 4164, SpvOpTensorWriteARM = 4165, SpvOpTensorQuerySizeARM = 4166, + SpvOpGraphConstantARM = 4181, + SpvOpGraphEntryPointARM = 4182, + SpvOpGraphARM = 4183, + SpvOpGraphInputARM = 4184, + SpvOpGraphSetOutputARM = 4185, + SpvOpGraphEndARM = 4186, + SpvOpTypeGraphARM = 4190, SpvOpTerminateInvocation = 4416, SpvOpTypeUntypedPointerKHR = 4417, SpvOpUntypedVariableKHR = 4418, @@ -1968,6 +1981,7 @@ typedef enum SpvOp_ { SpvOpGroupNonUniformRotateKHR = 4431, SpvOpSubgroupReadInvocationKHR = 4432, SpvOpExtInstWithForwardRefsKHR = 4433, + SpvOpUntypedGroupAsyncCopyKHR = 4434, SpvOpTraceRayKHR = 4445, SpvOpExecuteCallableKHR = 4446, SpvOpConvertUToAccelerationStructureKHR = 4447, @@ -2004,10 +2018,14 @@ typedef enum SpvOp_ { SpvOpImageBoxFilterQCOM = 4481, SpvOpImageBlockMatchSSDQCOM = 4482, SpvOpImageBlockMatchSADQCOM = 4483, + SpvOpBitCastArrayQCOM = 4497, SpvOpImageBlockMatchWindowSSDQCOM = 4500, SpvOpImageBlockMatchWindowSADQCOM = 4501, SpvOpImageBlockMatchGatherSSDQCOM = 4502, SpvOpImageBlockMatchGatherSADQCOM = 4503, + SpvOpCompositeConstructCoopMatQCOM = 4540, + SpvOpCompositeExtractCoopMatQCOM = 4541, + SpvOpExtractSubArrayQCOM = 4542, SpvOpGroupIAddNonUniformAMD = 5000, SpvOpGroupFAddNonUniformAMD = 5001, SpvOpGroupFMinNonUniformAMD = 5002, @@ -2089,6 +2107,7 @@ typedef enum SpvOp_ { SpvOpTypeAccelerationStructureNV = 5341, SpvOpExecuteCallableNV = 5344, SpvOpRayQueryGetClusterIdNV = 5345, + SpvOpRayQueryGetIntersectionClusterIdNV = 5345, SpvOpHitObjectGetClusterIdNV = 5346, SpvOpTypeCooperativeMatrixNV = 5358, SpvOpCooperativeMatrixLoadNV = 5359, @@ -2398,6 +2417,14 @@ typedef enum SpvOp_ { SpvOpSubgroup2DBlockStoreINTEL = 6235, SpvOpSubgroupMatrixMultiplyAccumulateINTEL = 6237, SpvOpBitwiseFunctionINTEL = 6242, + SpvOpUntypedVariableLengthArrayINTEL = 6244, + SpvOpConditionalExtensionINTEL = 6248, + SpvOpConditionalEntryPointINTEL = 6249, + SpvOpConditionalCapabilityINTEL = 6250, + SpvOpSpecConstantTargetINTEL = 6251, + SpvOpSpecConstantArchitectureINTEL = 6252, + SpvOpSpecConstantCapabilitiesINTEL = 6253, + SpvOpConditionalCopyObjectINTEL = 6254, SpvOpGroupIMulKHR = 6401, SpvOpGroupFMulKHR = 6402, SpvOpGroupBitwiseAndKHR = 6403, @@ -2774,6 +2801,13 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy case SpvOpTensorReadARM: *hasResult = true; *hasResultType = true; break; case SpvOpTensorWriteARM: *hasResult = false; *hasResultType = false; break; case SpvOpTensorQuerySizeARM: *hasResult = true; *hasResultType = true; break; + case SpvOpGraphConstantARM: *hasResult = true; *hasResultType = true; break; + case SpvOpGraphEntryPointARM: *hasResult = false; *hasResultType = false; break; + case SpvOpGraphARM: *hasResult = true; *hasResultType = true; break; + case SpvOpGraphInputARM: *hasResult = true; *hasResultType = true; break; + case SpvOpGraphSetOutputARM: *hasResult = false; *hasResultType = false; break; + case SpvOpGraphEndARM: *hasResult = false; *hasResultType = false; break; + case SpvOpTypeGraphARM: *hasResult = true; *hasResultType = false; break; case SpvOpTerminateInvocation: *hasResult = false; *hasResultType = false; break; case SpvOpTypeUntypedPointerKHR: *hasResult = true; *hasResultType = false; break; case SpvOpUntypedVariableKHR: *hasResult = true; *hasResultType = true; break; @@ -2791,6 +2825,7 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy case SpvOpGroupNonUniformRotateKHR: *hasResult = true; *hasResultType = true; break; case SpvOpSubgroupReadInvocationKHR: *hasResult = true; *hasResultType = true; break; case SpvOpExtInstWithForwardRefsKHR: *hasResult = true; *hasResultType = true; break; + case SpvOpUntypedGroupAsyncCopyKHR: *hasResult = true; *hasResultType = true; break; case SpvOpTraceRayKHR: *hasResult = false; *hasResultType = false; break; case SpvOpExecuteCallableKHR: *hasResult = false; *hasResultType = false; break; case SpvOpConvertUToAccelerationStructureKHR: *hasResult = true; *hasResultType = true; break; @@ -2821,10 +2856,14 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy case SpvOpImageBoxFilterQCOM: *hasResult = true; *hasResultType = true; break; case SpvOpImageBlockMatchSSDQCOM: *hasResult = true; *hasResultType = true; break; case SpvOpImageBlockMatchSADQCOM: *hasResult = true; *hasResultType = true; break; + case SpvOpBitCastArrayQCOM: *hasResult = true; *hasResultType = true; break; case SpvOpImageBlockMatchWindowSSDQCOM: *hasResult = true; *hasResultType = true; break; case SpvOpImageBlockMatchWindowSADQCOM: *hasResult = true; *hasResultType = true; break; case SpvOpImageBlockMatchGatherSSDQCOM: *hasResult = true; *hasResultType = true; break; case SpvOpImageBlockMatchGatherSADQCOM: *hasResult = true; *hasResultType = true; break; + case SpvOpCompositeConstructCoopMatQCOM: *hasResult = true; *hasResultType = true; break; + case SpvOpCompositeExtractCoopMatQCOM: *hasResult = true; *hasResultType = true; break; + case SpvOpExtractSubArrayQCOM: *hasResult = true; *hasResultType = true; break; case SpvOpGroupIAddNonUniformAMD: *hasResult = true; *hasResultType = true; break; case SpvOpGroupFAddNonUniformAMD: *hasResult = true; *hasResultType = true; break; case SpvOpGroupFMinNonUniformAMD: *hasResult = true; *hasResultType = true; break; @@ -2903,7 +2942,7 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy case SpvOpRayQueryGetIntersectionTriangleVertexPositionsKHR: *hasResult = true; *hasResultType = true; break; case SpvOpTypeAccelerationStructureKHR: *hasResult = true; *hasResultType = false; break; case SpvOpExecuteCallableNV: *hasResult = false; *hasResultType = false; break; - case SpvOpRayQueryGetClusterIdNV: *hasResult = true; *hasResultType = true; break; + case SpvOpRayQueryGetIntersectionClusterIdNV: *hasResult = true; *hasResultType = true; break; case SpvOpHitObjectGetClusterIdNV: *hasResult = true; *hasResultType = true; break; case SpvOpTypeCooperativeMatrixNV: *hasResult = true; *hasResultType = false; break; case SpvOpCooperativeMatrixLoadNV: *hasResult = true; *hasResultType = true; break; @@ -3210,6 +3249,14 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy case SpvOpSubgroup2DBlockStoreINTEL: *hasResult = false; *hasResultType = false; break; case SpvOpSubgroupMatrixMultiplyAccumulateINTEL: *hasResult = true; *hasResultType = true; break; case SpvOpBitwiseFunctionINTEL: *hasResult = true; *hasResultType = true; break; + case SpvOpUntypedVariableLengthArrayINTEL: *hasResult = true; *hasResultType = true; break; + case SpvOpConditionalExtensionINTEL: *hasResult = false; *hasResultType = false; break; + case SpvOpConditionalEntryPointINTEL: *hasResult = false; *hasResultType = false; break; + case SpvOpConditionalCapabilityINTEL: *hasResult = false; *hasResultType = false; break; + case SpvOpSpecConstantTargetINTEL: *hasResult = true; *hasResultType = true; break; + case SpvOpSpecConstantArchitectureINTEL: *hasResult = true; *hasResultType = true; break; + case SpvOpSpecConstantCapabilitiesINTEL: *hasResult = true; *hasResultType = true; break; + case SpvOpConditionalCopyObjectINTEL: *hasResult = true; *hasResultType = true; break; case SpvOpGroupIMulKHR: *hasResult = true; *hasResultType = true; break; case SpvOpGroupFMulKHR: *hasResult = true; *hasResultType = true; break; case SpvOpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break; @@ -3750,6 +3797,7 @@ inline const char* SpvDecorationToString(SpvDecoration value) { case SpvDecorationHostAccessINTEL: return "HostAccessINTEL"; case SpvDecorationInitModeINTEL: return "InitModeINTEL"; case SpvDecorationImplementInRegisterMapINTEL: return "ImplementInRegisterMapINTEL"; + case SpvDecorationConditionalINTEL: return "ConditionalINTEL"; case SpvDecorationCacheControlLoadINTEL: return "CacheControlLoadINTEL"; case SpvDecorationCacheControlStoreINTEL: return "CacheControlStoreINTEL"; default: return "Unknown"; @@ -4002,6 +4050,7 @@ inline const char* SpvCapabilityToString(SpvCapability value) { case SpvCapabilityTensorsARM: return "TensorsARM"; case SpvCapabilityStorageTensorArrayDynamicIndexingARM: return "StorageTensorArrayDynamicIndexingARM"; case SpvCapabilityStorageTensorArrayNonUniformIndexingARM: return "StorageTensorArrayNonUniformIndexingARM"; + case SpvCapabilityGraphARM: return "GraphARM"; case SpvCapabilityCooperativeMatrixLayoutsARM: return "CooperativeMatrixLayoutsARM"; case SpvCapabilityFloat8EXT: return "Float8EXT"; case SpvCapabilityFloat8CooperativeMatrixEXT: return "Float8CooperativeMatrixEXT"; @@ -4039,6 +4088,7 @@ inline const char* SpvCapabilityToString(SpvCapability value) { case SpvCapabilityTextureBoxFilterQCOM: return "TextureBoxFilterQCOM"; case SpvCapabilityTextureBlockMatchQCOM: return "TextureBlockMatchQCOM"; case SpvCapabilityTileShadingQCOM: return "TileShadingQCOM"; + case SpvCapabilityCooperativeMatrixConversionQCOM: return "CooperativeMatrixConversionQCOM"; case SpvCapabilityTextureBlockMatch2QCOM: return "TextureBlockMatch2QCOM"; case SpvCapabilityFloat16ImageAMD: return "Float16ImageAMD"; case SpvCapabilityImageGatherBiasLodAMD: return "ImageGatherBiasLodAMD"; @@ -4188,6 +4238,9 @@ inline const char* SpvCapabilityToString(SpvCapability value) { case SpvCapabilitySubgroup2DBlockTransposeINTEL: return "Subgroup2DBlockTransposeINTEL"; case SpvCapabilitySubgroupMatrixMultiplyAccumulateINTEL: return "SubgroupMatrixMultiplyAccumulateINTEL"; case SpvCapabilityTernaryBitwiseFunctionINTEL: return "TernaryBitwiseFunctionINTEL"; + case SpvCapabilityUntypedVariableLengthArrayINTEL: return "UntypedVariableLengthArrayINTEL"; + case SpvCapabilitySpecConditionalINTEL: return "SpecConditionalINTEL"; + case SpvCapabilityFunctionVariantsINTEL: return "FunctionVariantsINTEL"; case SpvCapabilityGroupUniformArithmeticKHR: return "GroupUniformArithmeticKHR"; case SpvCapabilityTensorFloat32RoundingINTEL: return "TensorFloat32RoundingINTEL"; case SpvCapabilityMaskedGatherScatterINTEL: return "MaskedGatherScatterINTEL"; @@ -4739,6 +4792,13 @@ inline const char* SpvOpToString(SpvOp value) { case SpvOpTensorReadARM: return "OpTensorReadARM"; case SpvOpTensorWriteARM: return "OpTensorWriteARM"; case SpvOpTensorQuerySizeARM: return "OpTensorQuerySizeARM"; + case SpvOpGraphConstantARM: return "OpGraphConstantARM"; + case SpvOpGraphEntryPointARM: return "OpGraphEntryPointARM"; + case SpvOpGraphARM: return "OpGraphARM"; + case SpvOpGraphInputARM: return "OpGraphInputARM"; + case SpvOpGraphSetOutputARM: return "OpGraphSetOutputARM"; + case SpvOpGraphEndARM: return "OpGraphEndARM"; + case SpvOpTypeGraphARM: return "OpTypeGraphARM"; case SpvOpTerminateInvocation: return "OpTerminateInvocation"; case SpvOpTypeUntypedPointerKHR: return "OpTypeUntypedPointerKHR"; case SpvOpUntypedVariableKHR: return "OpUntypedVariableKHR"; @@ -4756,6 +4816,7 @@ inline const char* SpvOpToString(SpvOp value) { case SpvOpGroupNonUniformRotateKHR: return "OpGroupNonUniformRotateKHR"; case SpvOpSubgroupReadInvocationKHR: return "OpSubgroupReadInvocationKHR"; case SpvOpExtInstWithForwardRefsKHR: return "OpExtInstWithForwardRefsKHR"; + case SpvOpUntypedGroupAsyncCopyKHR: return "OpUntypedGroupAsyncCopyKHR"; case SpvOpTraceRayKHR: return "OpTraceRayKHR"; case SpvOpExecuteCallableKHR: return "OpExecuteCallableKHR"; case SpvOpConvertUToAccelerationStructureKHR: return "OpConvertUToAccelerationStructureKHR"; @@ -4786,10 +4847,14 @@ inline const char* SpvOpToString(SpvOp value) { case SpvOpImageBoxFilterQCOM: return "OpImageBoxFilterQCOM"; case SpvOpImageBlockMatchSSDQCOM: return "OpImageBlockMatchSSDQCOM"; case SpvOpImageBlockMatchSADQCOM: return "OpImageBlockMatchSADQCOM"; + case SpvOpBitCastArrayQCOM: return "OpBitCastArrayQCOM"; case SpvOpImageBlockMatchWindowSSDQCOM: return "OpImageBlockMatchWindowSSDQCOM"; case SpvOpImageBlockMatchWindowSADQCOM: return "OpImageBlockMatchWindowSADQCOM"; case SpvOpImageBlockMatchGatherSSDQCOM: return "OpImageBlockMatchGatherSSDQCOM"; case SpvOpImageBlockMatchGatherSADQCOM: return "OpImageBlockMatchGatherSADQCOM"; + case SpvOpCompositeConstructCoopMatQCOM: return "OpCompositeConstructCoopMatQCOM"; + case SpvOpCompositeExtractCoopMatQCOM: return "OpCompositeExtractCoopMatQCOM"; + case SpvOpExtractSubArrayQCOM: return "OpExtractSubArrayQCOM"; case SpvOpGroupIAddNonUniformAMD: return "OpGroupIAddNonUniformAMD"; case SpvOpGroupFAddNonUniformAMD: return "OpGroupFAddNonUniformAMD"; case SpvOpGroupFMinNonUniformAMD: return "OpGroupFMinNonUniformAMD"; @@ -5175,6 +5240,14 @@ inline const char* SpvOpToString(SpvOp value) { case SpvOpSubgroup2DBlockStoreINTEL: return "OpSubgroup2DBlockStoreINTEL"; case SpvOpSubgroupMatrixMultiplyAccumulateINTEL: return "OpSubgroupMatrixMultiplyAccumulateINTEL"; case SpvOpBitwiseFunctionINTEL: return "OpBitwiseFunctionINTEL"; + case SpvOpUntypedVariableLengthArrayINTEL: return "OpUntypedVariableLengthArrayINTEL"; + case SpvOpConditionalExtensionINTEL: return "OpConditionalExtensionINTEL"; + case SpvOpConditionalEntryPointINTEL: return "OpConditionalEntryPointINTEL"; + case SpvOpConditionalCapabilityINTEL: return "OpConditionalCapabilityINTEL"; + case SpvOpSpecConstantTargetINTEL: return "OpSpecConstantTargetINTEL"; + case SpvOpSpecConstantArchitectureINTEL: return "OpSpecConstantArchitectureINTEL"; + case SpvOpSpecConstantCapabilitiesINTEL: return "OpSpecConstantCapabilitiesINTEL"; + case SpvOpConditionalCopyObjectINTEL: return "OpConditionalCopyObjectINTEL"; case SpvOpGroupIMulKHR: return "OpGroupIMulKHR"; case SpvOpGroupFMulKHR: return "OpGroupFMulKHR"; case SpvOpGroupBitwiseAndKHR: return "OpGroupBitwiseAndKHR"; diff --git a/3rdparty/spirv-headers/include/spirv/unified1/spirv.hpp11 b/3rdparty/spirv-headers/include/spirv/unified1/spirv.hpp11 index f77374aec..6c287888c 100644 --- a/3rdparty/spirv-headers/include/spirv/unified1/spirv.hpp11 +++ b/3rdparty/spirv-headers/include/spirv/unified1/spirv.hpp11 @@ -638,6 +638,7 @@ enum class Decoration : unsigned { HostAccessINTEL = 6188, InitModeINTEL = 6190, ImplementInRegisterMapINTEL = 6191, + ConditionalINTEL = 6247, CacheControlLoadINTEL = 6442, CacheControlStoreINTEL = 6443, Max = 0x7fffffff, @@ -1063,6 +1064,7 @@ enum class Capability : unsigned { TensorsARM = 4174, StorageTensorArrayDynamicIndexingARM = 4175, StorageTensorArrayNonUniformIndexingARM = 4176, + GraphARM = 4191, CooperativeMatrixLayoutsARM = 4201, Float8EXT = 4212, Float8CooperativeMatrixEXT = 4213, @@ -1102,6 +1104,7 @@ enum class Capability : unsigned { TextureBoxFilterQCOM = 4485, TextureBlockMatchQCOM = 4486, TileShadingQCOM = 4495, + CooperativeMatrixConversionQCOM = 4496, TextureBlockMatch2QCOM = 4498, Float16ImageAMD = 5008, ImageGatherBiasLodAMD = 5009, @@ -1277,6 +1280,9 @@ enum class Capability : unsigned { Subgroup2DBlockTransposeINTEL = 6230, SubgroupMatrixMultiplyAccumulateINTEL = 6236, TernaryBitwiseFunctionINTEL = 6241, + UntypedVariableLengthArrayINTEL = 6243, + SpecConditionalINTEL = 6245, + FunctionVariantsINTEL = 6246, GroupUniformArithmeticKHR = 6400, TensorFloat32RoundingINTEL = 6425, MaskedGatherScatterINTEL = 6427, @@ -1947,6 +1953,13 @@ enum class Op : unsigned { OpTensorReadARM = 4164, OpTensorWriteARM = 4165, OpTensorQuerySizeARM = 4166, + OpGraphConstantARM = 4181, + OpGraphEntryPointARM = 4182, + OpGraphARM = 4183, + OpGraphInputARM = 4184, + OpGraphSetOutputARM = 4185, + OpGraphEndARM = 4186, + OpTypeGraphARM = 4190, OpTerminateInvocation = 4416, OpTypeUntypedPointerKHR = 4417, OpUntypedVariableKHR = 4418, @@ -1964,6 +1977,7 @@ enum class Op : unsigned { OpGroupNonUniformRotateKHR = 4431, OpSubgroupReadInvocationKHR = 4432, OpExtInstWithForwardRefsKHR = 4433, + OpUntypedGroupAsyncCopyKHR = 4434, OpTraceRayKHR = 4445, OpExecuteCallableKHR = 4446, OpConvertUToAccelerationStructureKHR = 4447, @@ -2000,10 +2014,14 @@ enum class Op : unsigned { OpImageBoxFilterQCOM = 4481, OpImageBlockMatchSSDQCOM = 4482, OpImageBlockMatchSADQCOM = 4483, + OpBitCastArrayQCOM = 4497, OpImageBlockMatchWindowSSDQCOM = 4500, OpImageBlockMatchWindowSADQCOM = 4501, OpImageBlockMatchGatherSSDQCOM = 4502, OpImageBlockMatchGatherSADQCOM = 4503, + OpCompositeConstructCoopMatQCOM = 4540, + OpCompositeExtractCoopMatQCOM = 4541, + OpExtractSubArrayQCOM = 4542, OpGroupIAddNonUniformAMD = 5000, OpGroupFAddNonUniformAMD = 5001, OpGroupFMinNonUniformAMD = 5002, @@ -2085,6 +2103,7 @@ enum class Op : unsigned { OpTypeAccelerationStructureNV = 5341, OpExecuteCallableNV = 5344, OpRayQueryGetClusterIdNV = 5345, + OpRayQueryGetIntersectionClusterIdNV = 5345, OpHitObjectGetClusterIdNV = 5346, OpTypeCooperativeMatrixNV = 5358, OpCooperativeMatrixLoadNV = 5359, @@ -2394,6 +2413,14 @@ enum class Op : unsigned { OpSubgroup2DBlockStoreINTEL = 6235, OpSubgroupMatrixMultiplyAccumulateINTEL = 6237, OpBitwiseFunctionINTEL = 6242, + OpUntypedVariableLengthArrayINTEL = 6244, + OpConditionalExtensionINTEL = 6248, + OpConditionalEntryPointINTEL = 6249, + OpConditionalCapabilityINTEL = 6250, + OpSpecConstantTargetINTEL = 6251, + OpSpecConstantArchitectureINTEL = 6252, + OpSpecConstantCapabilitiesINTEL = 6253, + OpConditionalCopyObjectINTEL = 6254, OpGroupIMulKHR = 6401, OpGroupFMulKHR = 6402, OpGroupBitwiseAndKHR = 6403, @@ -2770,6 +2797,13 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) { case Op::OpTensorReadARM: *hasResult = true; *hasResultType = true; break; case Op::OpTensorWriteARM: *hasResult = false; *hasResultType = false; break; case Op::OpTensorQuerySizeARM: *hasResult = true; *hasResultType = true; break; + case Op::OpGraphConstantARM: *hasResult = true; *hasResultType = true; break; + case Op::OpGraphEntryPointARM: *hasResult = false; *hasResultType = false; break; + case Op::OpGraphARM: *hasResult = true; *hasResultType = true; break; + case Op::OpGraphInputARM: *hasResult = true; *hasResultType = true; break; + case Op::OpGraphSetOutputARM: *hasResult = false; *hasResultType = false; break; + case Op::OpGraphEndARM: *hasResult = false; *hasResultType = false; break; + case Op::OpTypeGraphARM: *hasResult = true; *hasResultType = false; break; case Op::OpTerminateInvocation: *hasResult = false; *hasResultType = false; break; case Op::OpTypeUntypedPointerKHR: *hasResult = true; *hasResultType = false; break; case Op::OpUntypedVariableKHR: *hasResult = true; *hasResultType = true; break; @@ -2787,6 +2821,7 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) { case Op::OpGroupNonUniformRotateKHR: *hasResult = true; *hasResultType = true; break; case Op::OpSubgroupReadInvocationKHR: *hasResult = true; *hasResultType = true; break; case Op::OpExtInstWithForwardRefsKHR: *hasResult = true; *hasResultType = true; break; + case Op::OpUntypedGroupAsyncCopyKHR: *hasResult = true; *hasResultType = true; break; case Op::OpTraceRayKHR: *hasResult = false; *hasResultType = false; break; case Op::OpExecuteCallableKHR: *hasResult = false; *hasResultType = false; break; case Op::OpConvertUToAccelerationStructureKHR: *hasResult = true; *hasResultType = true; break; @@ -2817,10 +2852,14 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) { case Op::OpImageBoxFilterQCOM: *hasResult = true; *hasResultType = true; break; case Op::OpImageBlockMatchSSDQCOM: *hasResult = true; *hasResultType = true; break; case Op::OpImageBlockMatchSADQCOM: *hasResult = true; *hasResultType = true; break; + case Op::OpBitCastArrayQCOM: *hasResult = true; *hasResultType = true; break; case Op::OpImageBlockMatchWindowSSDQCOM: *hasResult = true; *hasResultType = true; break; case Op::OpImageBlockMatchWindowSADQCOM: *hasResult = true; *hasResultType = true; break; case Op::OpImageBlockMatchGatherSSDQCOM: *hasResult = true; *hasResultType = true; break; case Op::OpImageBlockMatchGatherSADQCOM: *hasResult = true; *hasResultType = true; break; + case Op::OpCompositeConstructCoopMatQCOM: *hasResult = true; *hasResultType = true; break; + case Op::OpCompositeExtractCoopMatQCOM: *hasResult = true; *hasResultType = true; break; + case Op::OpExtractSubArrayQCOM: *hasResult = true; *hasResultType = true; break; case Op::OpGroupIAddNonUniformAMD: *hasResult = true; *hasResultType = true; break; case Op::OpGroupFAddNonUniformAMD: *hasResult = true; *hasResultType = true; break; case Op::OpGroupFMinNonUniformAMD: *hasResult = true; *hasResultType = true; break; @@ -2899,7 +2938,7 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) { case Op::OpRayQueryGetIntersectionTriangleVertexPositionsKHR: *hasResult = true; *hasResultType = true; break; case Op::OpTypeAccelerationStructureKHR: *hasResult = true; *hasResultType = false; break; case Op::OpExecuteCallableNV: *hasResult = false; *hasResultType = false; break; - case Op::OpRayQueryGetClusterIdNV: *hasResult = true; *hasResultType = true; break; + case Op::OpRayQueryGetIntersectionClusterIdNV: *hasResult = true; *hasResultType = true; break; case Op::OpHitObjectGetClusterIdNV: *hasResult = true; *hasResultType = true; break; case Op::OpTypeCooperativeMatrixNV: *hasResult = true; *hasResultType = false; break; case Op::OpCooperativeMatrixLoadNV: *hasResult = true; *hasResultType = true; break; @@ -3206,6 +3245,14 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) { case Op::OpSubgroup2DBlockStoreINTEL: *hasResult = false; *hasResultType = false; break; case Op::OpSubgroupMatrixMultiplyAccumulateINTEL: *hasResult = true; *hasResultType = true; break; case Op::OpBitwiseFunctionINTEL: *hasResult = true; *hasResultType = true; break; + case Op::OpUntypedVariableLengthArrayINTEL: *hasResult = true; *hasResultType = true; break; + case Op::OpConditionalExtensionINTEL: *hasResult = false; *hasResultType = false; break; + case Op::OpConditionalEntryPointINTEL: *hasResult = false; *hasResultType = false; break; + case Op::OpConditionalCapabilityINTEL: *hasResult = false; *hasResultType = false; break; + case Op::OpSpecConstantTargetINTEL: *hasResult = true; *hasResultType = true; break; + case Op::OpSpecConstantArchitectureINTEL: *hasResult = true; *hasResultType = true; break; + case Op::OpSpecConstantCapabilitiesINTEL: *hasResult = true; *hasResultType = true; break; + case Op::OpConditionalCopyObjectINTEL: *hasResult = true; *hasResultType = true; break; case Op::OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break; case Op::OpGroupFMulKHR: *hasResult = true; *hasResultType = true; break; case Op::OpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break; @@ -3746,6 +3793,7 @@ inline const char* DecorationToString(Decoration value) { case Decoration::HostAccessINTEL: return "HostAccessINTEL"; case Decoration::InitModeINTEL: return "InitModeINTEL"; case Decoration::ImplementInRegisterMapINTEL: return "ImplementInRegisterMapINTEL"; + case Decoration::ConditionalINTEL: return "ConditionalINTEL"; case Decoration::CacheControlLoadINTEL: return "CacheControlLoadINTEL"; case Decoration::CacheControlStoreINTEL: return "CacheControlStoreINTEL"; default: return "Unknown"; @@ -3998,6 +4046,7 @@ inline const char* CapabilityToString(Capability value) { case Capability::TensorsARM: return "TensorsARM"; case Capability::StorageTensorArrayDynamicIndexingARM: return "StorageTensorArrayDynamicIndexingARM"; case Capability::StorageTensorArrayNonUniformIndexingARM: return "StorageTensorArrayNonUniformIndexingARM"; + case Capability::GraphARM: return "GraphARM"; case Capability::CooperativeMatrixLayoutsARM: return "CooperativeMatrixLayoutsARM"; case Capability::Float8EXT: return "Float8EXT"; case Capability::Float8CooperativeMatrixEXT: return "Float8CooperativeMatrixEXT"; @@ -4035,6 +4084,7 @@ inline const char* CapabilityToString(Capability value) { case Capability::TextureBoxFilterQCOM: return "TextureBoxFilterQCOM"; case Capability::TextureBlockMatchQCOM: return "TextureBlockMatchQCOM"; case Capability::TileShadingQCOM: return "TileShadingQCOM"; + case Capability::CooperativeMatrixConversionQCOM: return "CooperativeMatrixConversionQCOM"; case Capability::TextureBlockMatch2QCOM: return "TextureBlockMatch2QCOM"; case Capability::Float16ImageAMD: return "Float16ImageAMD"; case Capability::ImageGatherBiasLodAMD: return "ImageGatherBiasLodAMD"; @@ -4184,6 +4234,9 @@ inline const char* CapabilityToString(Capability value) { case Capability::Subgroup2DBlockTransposeINTEL: return "Subgroup2DBlockTransposeINTEL"; case Capability::SubgroupMatrixMultiplyAccumulateINTEL: return "SubgroupMatrixMultiplyAccumulateINTEL"; case Capability::TernaryBitwiseFunctionINTEL: return "TernaryBitwiseFunctionINTEL"; + case Capability::UntypedVariableLengthArrayINTEL: return "UntypedVariableLengthArrayINTEL"; + case Capability::SpecConditionalINTEL: return "SpecConditionalINTEL"; + case Capability::FunctionVariantsINTEL: return "FunctionVariantsINTEL"; case Capability::GroupUniformArithmeticKHR: return "GroupUniformArithmeticKHR"; case Capability::TensorFloat32RoundingINTEL: return "TensorFloat32RoundingINTEL"; case Capability::MaskedGatherScatterINTEL: return "MaskedGatherScatterINTEL"; @@ -4735,6 +4788,13 @@ inline const char* OpToString(Op value) { case Op::OpTensorReadARM: return "OpTensorReadARM"; case Op::OpTensorWriteARM: return "OpTensorWriteARM"; case Op::OpTensorQuerySizeARM: return "OpTensorQuerySizeARM"; + case Op::OpGraphConstantARM: return "OpGraphConstantARM"; + case Op::OpGraphEntryPointARM: return "OpGraphEntryPointARM"; + case Op::OpGraphARM: return "OpGraphARM"; + case Op::OpGraphInputARM: return "OpGraphInputARM"; + case Op::OpGraphSetOutputARM: return "OpGraphSetOutputARM"; + case Op::OpGraphEndARM: return "OpGraphEndARM"; + case Op::OpTypeGraphARM: return "OpTypeGraphARM"; case Op::OpTerminateInvocation: return "OpTerminateInvocation"; case Op::OpTypeUntypedPointerKHR: return "OpTypeUntypedPointerKHR"; case Op::OpUntypedVariableKHR: return "OpUntypedVariableKHR"; @@ -4752,6 +4812,7 @@ inline const char* OpToString(Op value) { case Op::OpGroupNonUniformRotateKHR: return "OpGroupNonUniformRotateKHR"; case Op::OpSubgroupReadInvocationKHR: return "OpSubgroupReadInvocationKHR"; case Op::OpExtInstWithForwardRefsKHR: return "OpExtInstWithForwardRefsKHR"; + case Op::OpUntypedGroupAsyncCopyKHR: return "OpUntypedGroupAsyncCopyKHR"; case Op::OpTraceRayKHR: return "OpTraceRayKHR"; case Op::OpExecuteCallableKHR: return "OpExecuteCallableKHR"; case Op::OpConvertUToAccelerationStructureKHR: return "OpConvertUToAccelerationStructureKHR"; @@ -4782,10 +4843,14 @@ inline const char* OpToString(Op value) { case Op::OpImageBoxFilterQCOM: return "OpImageBoxFilterQCOM"; case Op::OpImageBlockMatchSSDQCOM: return "OpImageBlockMatchSSDQCOM"; case Op::OpImageBlockMatchSADQCOM: return "OpImageBlockMatchSADQCOM"; + case Op::OpBitCastArrayQCOM: return "OpBitCastArrayQCOM"; case Op::OpImageBlockMatchWindowSSDQCOM: return "OpImageBlockMatchWindowSSDQCOM"; case Op::OpImageBlockMatchWindowSADQCOM: return "OpImageBlockMatchWindowSADQCOM"; case Op::OpImageBlockMatchGatherSSDQCOM: return "OpImageBlockMatchGatherSSDQCOM"; case Op::OpImageBlockMatchGatherSADQCOM: return "OpImageBlockMatchGatherSADQCOM"; + case Op::OpCompositeConstructCoopMatQCOM: return "OpCompositeConstructCoopMatQCOM"; + case Op::OpCompositeExtractCoopMatQCOM: return "OpCompositeExtractCoopMatQCOM"; + case Op::OpExtractSubArrayQCOM: return "OpExtractSubArrayQCOM"; case Op::OpGroupIAddNonUniformAMD: return "OpGroupIAddNonUniformAMD"; case Op::OpGroupFAddNonUniformAMD: return "OpGroupFAddNonUniformAMD"; case Op::OpGroupFMinNonUniformAMD: return "OpGroupFMinNonUniformAMD"; @@ -5171,6 +5236,14 @@ inline const char* OpToString(Op value) { case Op::OpSubgroup2DBlockStoreINTEL: return "OpSubgroup2DBlockStoreINTEL"; case Op::OpSubgroupMatrixMultiplyAccumulateINTEL: return "OpSubgroupMatrixMultiplyAccumulateINTEL"; case Op::OpBitwiseFunctionINTEL: return "OpBitwiseFunctionINTEL"; + case Op::OpUntypedVariableLengthArrayINTEL: return "OpUntypedVariableLengthArrayINTEL"; + case Op::OpConditionalExtensionINTEL: return "OpConditionalExtensionINTEL"; + case Op::OpConditionalEntryPointINTEL: return "OpConditionalEntryPointINTEL"; + case Op::OpConditionalCapabilityINTEL: return "OpConditionalCapabilityINTEL"; + case Op::OpSpecConstantTargetINTEL: return "OpSpecConstantTargetINTEL"; + case Op::OpSpecConstantArchitectureINTEL: return "OpSpecConstantArchitectureINTEL"; + case Op::OpSpecConstantCapabilitiesINTEL: return "OpSpecConstantCapabilitiesINTEL"; + case Op::OpConditionalCopyObjectINTEL: return "OpConditionalCopyObjectINTEL"; case Op::OpGroupIMulKHR: return "OpGroupIMulKHR"; case Op::OpGroupFMulKHR: return "OpGroupFMulKHR"; case Op::OpGroupBitwiseAndKHR: return "OpGroupBitwiseAndKHR"; diff --git a/3rdparty/spirv-headers/include/spirv/unified1/spirv.json b/3rdparty/spirv-headers/include/spirv/unified1/spirv.json index db7ae255c..5ee68505a 100644 --- a/3rdparty/spirv-headers/include/spirv/unified1/spirv.json +++ b/3rdparty/spirv-headers/include/spirv/unified1/spirv.json @@ -661,6 +661,7 @@ "HostAccessINTEL": 6188, "InitModeINTEL": 6190, "ImplementInRegisterMapINTEL": 6191, + "ConditionalINTEL": 6247, "CacheControlLoadINTEL": 6442, "CacheControlStoreINTEL": 6443 } @@ -1039,6 +1040,7 @@ "TensorsARM": 4174, "StorageTensorArrayDynamicIndexingARM": 4175, "StorageTensorArrayNonUniformIndexingARM": 4176, + "GraphARM": 4191, "CooperativeMatrixLayoutsARM": 4201, "Float8EXT": 4212, "Float8CooperativeMatrixEXT": 4213, @@ -1078,6 +1080,7 @@ "TextureBoxFilterQCOM": 4485, "TextureBlockMatchQCOM": 4486, "TileShadingQCOM": 4495, + "CooperativeMatrixConversionQCOM": 4496, "TextureBlockMatch2QCOM": 4498, "Float16ImageAMD": 5008, "ImageGatherBiasLodAMD": 5009, @@ -1253,6 +1256,9 @@ "Subgroup2DBlockTransposeINTEL": 6230, "SubgroupMatrixMultiplyAccumulateINTEL": 6236, "TernaryBitwiseFunctionINTEL": 6241, + "UntypedVariableLengthArrayINTEL": 6243, + "SpecConditionalINTEL": 6245, + "FunctionVariantsINTEL": 6246, "GroupUniformArithmeticKHR": 6400, "TensorFloat32RoundingINTEL": 6425, "MaskedGatherScatterINTEL": 6427, @@ -1928,6 +1934,13 @@ "OpTensorReadARM": 4164, "OpTensorWriteARM": 4165, "OpTensorQuerySizeARM": 4166, + "OpGraphConstantARM": 4181, + "OpGraphEntryPointARM": 4182, + "OpGraphARM": 4183, + "OpGraphInputARM": 4184, + "OpGraphSetOutputARM": 4185, + "OpGraphEndARM": 4186, + "OpTypeGraphARM": 4190, "OpTerminateInvocation": 4416, "OpTypeUntypedPointerKHR": 4417, "OpUntypedVariableKHR": 4418, @@ -1945,6 +1958,7 @@ "OpGroupNonUniformRotateKHR": 4431, "OpSubgroupReadInvocationKHR": 4432, "OpExtInstWithForwardRefsKHR": 4433, + "OpUntypedGroupAsyncCopyKHR": 4434, "OpTraceRayKHR": 4445, "OpExecuteCallableKHR": 4446, "OpConvertUToAccelerationStructureKHR": 4447, @@ -1981,10 +1995,14 @@ "OpImageBoxFilterQCOM": 4481, "OpImageBlockMatchSSDQCOM": 4482, "OpImageBlockMatchSADQCOM": 4483, + "OpBitCastArrayQCOM": 4497, "OpImageBlockMatchWindowSSDQCOM": 4500, "OpImageBlockMatchWindowSADQCOM": 4501, "OpImageBlockMatchGatherSSDQCOM": 4502, "OpImageBlockMatchGatherSADQCOM": 4503, + "OpCompositeConstructCoopMatQCOM": 4540, + "OpCompositeExtractCoopMatQCOM": 4541, + "OpExtractSubArrayQCOM": 4542, "OpGroupIAddNonUniformAMD": 5000, "OpGroupFAddNonUniformAMD": 5001, "OpGroupFMinNonUniformAMD": 5002, @@ -2066,6 +2084,7 @@ "OpTypeAccelerationStructureNV": 5341, "OpExecuteCallableNV": 5344, "OpRayQueryGetClusterIdNV": 5345, + "OpRayQueryGetIntersectionClusterIdNV": 5345, "OpHitObjectGetClusterIdNV": 5346, "OpTypeCooperativeMatrixNV": 5358, "OpCooperativeMatrixLoadNV": 5359, @@ -2375,6 +2394,14 @@ "OpSubgroup2DBlockStoreINTEL": 6235, "OpSubgroupMatrixMultiplyAccumulateINTEL": 6237, "OpBitwiseFunctionINTEL": 6242, + "OpUntypedVariableLengthArrayINTEL": 6244, + "OpConditionalExtensionINTEL": 6248, + "OpConditionalEntryPointINTEL": 6249, + "OpConditionalCapabilityINTEL": 6250, + "OpSpecConstantTargetINTEL": 6251, + "OpSpecConstantArchitectureINTEL": 6252, + "OpSpecConstantCapabilitiesINTEL": 6253, + "OpConditionalCopyObjectINTEL": 6254, "OpGroupIMulKHR": 6401, "OpGroupFMulKHR": 6402, "OpGroupBitwiseAndKHR": 6403,