diff --git a/3rdparty/spirv-headers/include/spirv/unified1/spirv.core.grammar.json b/3rdparty/spirv-headers/include/spirv/unified1/spirv.core.grammar.json index 4dc955ef5..4de8edc24 100644 --- a/3rdparty/spirv-headers/include/spirv/unified1/spirv.core.grammar.json +++ b/3rdparty/spirv-headers/include/spirv/unified1/spirv.core.grammar.json @@ -4856,7 +4856,7 @@ }, { "opname" : "OpTypeRayQueryKHR", - "class" : "Reserved", + "class" : "Type-Declaration", "opcode" : 4472, "operands" : [ { "kind" : "IdResult" } @@ -5693,7 +5693,7 @@ }, { "opname" : "OpTypeHitObjectNV", - "class" : "Reserved", + "class" : "Type-Declaration", "opcode" : 5281, "operands" : [ { "kind" : "IdResult" } @@ -5932,7 +5932,7 @@ }, { "opname" : "OpTypeAccelerationStructureNV", - "class" : "Reserved", + "class" : "Type-Declaration", "opcode" : 5341, "operands" : [ { "kind" : "IdResult" } @@ -5943,7 +5943,7 @@ }, { "opname" : "OpTypeAccelerationStructureKHR", - "class" : "Reserved", + "class" : "Type-Declaration", "opcode" : 5341, "operands" : [ { "kind" : "IdResult" } @@ -5967,7 +5967,7 @@ }, { "opname" : "OpTypeCooperativeMatrixNV", - "class" : "Reserved", + "class" : "Type-Declaration", "opcode" : 5358, "operands" : [ { "kind" : "IdResult" }, @@ -9564,7 +9564,7 @@ "operands" : [ { "kind" : "IdRef", "quantifier" : "*", "name" : "'Member 0 type', +\n'member 1 type', +\n..." } ], - "capabilities" : [ "LongConstantCompositeINTEL" ], + "capabilities" : [ "LongCompositesINTEL" ], "version" : "None" }, { @@ -9574,7 +9574,7 @@ "operands" : [ { "kind" : "IdRef", "quantifier" : "*", "name" : "'Constituents'" } ], - "capabilities" : [ "LongConstantCompositeINTEL" ], + "capabilities" : [ "LongCompositesINTEL" ], "version" : "None" }, { @@ -9584,9 +9584,21 @@ "operands" : [ { "kind" : "IdRef", "quantifier" : "*", "name" : "'Constituents'" } ], - "capabilities" : [ "LongConstantCompositeINTEL" ], + "capabilities" : [ "LongCompositesINTEL" ], "version" : "None" }, + { + "opname" : "OpCompositeConstructContinuedINTEL", + "class" : "Composite", + "opcode" : 6096, + "operands" : [ + { "kind" : "IdResultType" }, + { "kind" : "IdResult" }, + { "kind" : "IdRef", "quantifier" : "*", "name" : "'Constituents'" } + ], + "capabilities" : [ "LongCompositesINTEL" ], + "version": "None" + }, { "opname" : "OpConvertFToBF16INTEL", "class" : "Conversion", @@ -13567,6 +13579,12 @@ "capabilities" : [ "VectorComputeINTEL" ], "version" : "None" }, + { + "enumerant" : "StallFreeINTEL", + "value" : 6151, + "capabilities" : [ "FPGAClusterAttributesV2INTEL" ], + "version" : "None" + }, { "enumerant" : "FPMaxErrorDecorationINTEL", "value" : 6170, @@ -16224,9 +16242,9 @@ "version" : "None" }, { - "enumerant" : "LongConstantCompositeINTEL", + "enumerant" : "LongCompositesINTEL", "value" : 6089, - "extensions" : [ "SPV_INTEL_long_constant_composite" ], + "extensions" : [ "SPV_INTEL_long_composites" ], "version" : "None" }, { @@ -16259,6 +16277,13 @@ "extensions" : [ "SPV_INTEL_split_barrier" ], "version" : "None" }, + { + "enumerant" : "FPGAClusterAttributesV2INTEL", + "value" : 6150, + "capabilities" : [ "FPGAClusterAttributesINTEL" ], + "extensions" : [ "SPV_INTEL_fpga_cluster_attributes" ], + "version" : "None" + }, { "enumerant" : "FPGAKernelAttributesv2INTEL", "value" : 6161, diff --git a/3rdparty/spirv-headers/include/spirv/unified1/spirv.h b/3rdparty/spirv-headers/include/spirv/unified1/spirv.h index a1718715d..58b193268 100644 --- a/3rdparty/spirv-headers/include/spirv/unified1/spirv.h +++ b/3rdparty/spirv-headers/include/spirv/unified1/spirv.h @@ -608,6 +608,7 @@ typedef enum SpvDecoration_ { SpvDecorationSingleElementVectorINTEL = 6085, SpvDecorationVectorComputeCallableFunctionINTEL = 6087, SpvDecorationMediaBlockIOINTEL = 6140, + SpvDecorationStallFreeINTEL = 6151, SpvDecorationFPMaxErrorDecorationINTEL = 6170, SpvDecorationLatencyControlLabelINTEL = 6172, SpvDecorationLatencyControlConstraintINTEL = 6173, @@ -1196,12 +1197,13 @@ typedef enum SpvCapability_ { SpvCapabilityGroupNonUniformRotateKHR = 6026, SpvCapabilityAtomicFloat32AddEXT = 6033, SpvCapabilityAtomicFloat64AddEXT = 6034, - SpvCapabilityLongConstantCompositeINTEL = 6089, + SpvCapabilityLongCompositesINTEL = 6089, SpvCapabilityOptNoneINTEL = 6094, SpvCapabilityAtomicFloat16AddEXT = 6095, SpvCapabilityDebugInfoModuleINTEL = 6114, SpvCapabilityBFloat16ConversionINTEL = 6115, SpvCapabilitySplitBarrierINTEL = 6141, + SpvCapabilityFPGAClusterAttributesV2INTEL = 6150, SpvCapabilityFPGAKernelAttributesv2INTEL = 6161, SpvCapabilityFPMaxErrorINTEL = 6169, SpvCapabilityFPGALatencyControlINTEL = 6171, @@ -2090,6 +2092,7 @@ typedef enum SpvOp_ { SpvOpTypeStructContinuedINTEL = 6090, SpvOpConstantCompositeContinuedINTEL = 6091, SpvOpSpecConstantCompositeContinuedINTEL = 6092, + SpvOpCompositeConstructContinuedINTEL = 6096, SpvOpConvertFToBF16INTEL = 6116, SpvOpConvertBF16ToFINTEL = 6117, SpvOpControlBarrierArriveINTEL = 6142, @@ -2813,6 +2816,7 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy case SpvOpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break; case SpvOpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break; case SpvOpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break; + case SpvOpCompositeConstructContinuedINTEL: *hasResult = true; *hasResultType = true; break; case SpvOpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break; case SpvOpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break; case SpvOpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break; diff --git a/3rdparty/spirv-headers/include/spirv/unified1/spirv.hpp11 b/3rdparty/spirv-headers/include/spirv/unified1/spirv.hpp11 index e49e491e3..cc2590c77 100644 --- a/3rdparty/spirv-headers/include/spirv/unified1/spirv.hpp11 +++ b/3rdparty/spirv-headers/include/spirv/unified1/spirv.hpp11 @@ -604,6 +604,7 @@ enum class Decoration : unsigned { SingleElementVectorINTEL = 6085, VectorComputeCallableFunctionINTEL = 6087, MediaBlockIOINTEL = 6140, + StallFreeINTEL = 6151, FPMaxErrorDecorationINTEL = 6170, LatencyControlLabelINTEL = 6172, LatencyControlConstraintINTEL = 6173, @@ -1192,12 +1193,13 @@ enum class Capability : unsigned { GroupNonUniformRotateKHR = 6026, AtomicFloat32AddEXT = 6033, AtomicFloat64AddEXT = 6034, - LongConstantCompositeINTEL = 6089, + LongCompositesINTEL = 6089, OptNoneINTEL = 6094, AtomicFloat16AddEXT = 6095, DebugInfoModuleINTEL = 6114, BFloat16ConversionINTEL = 6115, SplitBarrierINTEL = 6141, + FPGAClusterAttributesV2INTEL = 6150, FPGAKernelAttributesv2INTEL = 6161, FPMaxErrorINTEL = 6169, FPGALatencyControlINTEL = 6171, @@ -2086,6 +2088,7 @@ enum class Op : unsigned { OpTypeStructContinuedINTEL = 6090, OpConstantCompositeContinuedINTEL = 6091, OpSpecConstantCompositeContinuedINTEL = 6092, + OpCompositeConstructContinuedINTEL = 6096, OpConvertFToBF16INTEL = 6116, OpConvertBF16ToFINTEL = 6117, OpControlBarrierArriveINTEL = 6142, @@ -2809,6 +2812,7 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) { case Op::OpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break; case Op::OpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break; case Op::OpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break; + case Op::OpCompositeConstructContinuedINTEL: *hasResult = true; *hasResultType = true; break; case Op::OpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break; case Op::OpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break; case Op::OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break; diff --git a/3rdparty/spirv-headers/include/spirv/unified1/spirv.json b/3rdparty/spirv-headers/include/spirv/unified1/spirv.json index f1ad055aa..505db1fcd 100644 --- a/3rdparty/spirv-headers/include/spirv/unified1/spirv.json +++ b/3rdparty/spirv-headers/include/spirv/unified1/spirv.json @@ -630,6 +630,7 @@ "SingleElementVectorINTEL": 6085, "VectorComputeCallableFunctionINTEL": 6087, "MediaBlockIOINTEL": 6140, + "StallFreeINTEL": 6151, "FPMaxErrorDecorationINTEL": 6170, "LatencyControlLabelINTEL": 6172, "LatencyControlConstraintINTEL": 6173, @@ -1172,12 +1173,13 @@ "GroupNonUniformRotateKHR": 6026, "AtomicFloat32AddEXT": 6033, "AtomicFloat64AddEXT": 6034, - "LongConstantCompositeINTEL": 6089, + "LongCompositesINTEL": 6089, "OptNoneINTEL": 6094, "AtomicFloat16AddEXT": 6095, "DebugInfoModuleINTEL": 6114, "BFloat16ConversionINTEL": 6115, "SplitBarrierINTEL": 6141, + "FPGAClusterAttributesV2INTEL": 6150, "FPGAKernelAttributesv2INTEL": 6161, "FPMaxErrorINTEL": 6169, "FPGALatencyControlINTEL": 6171, @@ -2088,6 +2090,7 @@ "OpTypeStructContinuedINTEL": 6090, "OpConstantCompositeContinuedINTEL": 6091, "OpSpecConstantCompositeContinuedINTEL": 6092, + "OpCompositeConstructContinuedINTEL": 6096, "OpConvertFToBF16INTEL": 6116, "OpConvertBF16ToFINTEL": 6117, "OpControlBarrierArriveINTEL": 6142,