Updated spirv-headers.

2026-02-17 20:52:36 +01:00 · 2023-09-04 08:25:04 -07:00
parent cc33a884ff
commit 04b0560edb
4 changed files with 1694 additions and 680 deletions
--- a/3rdparty/spirv-headers/include/spirv/unified1/spirv.core.grammar.json
+++ b/3rdparty/spirv-headers/include/spirv/unified1/spirv.core.grammar.json
--- a/3rdparty/spirv-headers/include/spirv/unified1/spirv.h
+++ b/3rdparty/spirv-headers/include/spirv/unified1/spirv.h
@@ -175,6 +175,11 @@ typedef enum SpvExecutionMode_ {
    SpvExecutionModeRoundingModeRTZ = 4463,
    SpvExecutionModeEarlyAndLateFragmentTestsAMD = 5017,
    SpvExecutionModeStencilRefReplacingEXT = 5027,
+    SpvExecutionModeCoalescingAMDX = 5069,
+    SpvExecutionModeMaxNodeRecursionAMDX = 5071,
+    SpvExecutionModeStaticNumWorkgroupsAMDX = 5072,
+    SpvExecutionModeShaderIndexAMDX = 5073,
+    SpvExecutionModeMaxNumWorkgroupsAMDX = 5077,
    SpvExecutionModeStencilRefUnchangedFrontAMD = 5079,
    SpvExecutionModeStencilRefGreaterFrontAMD = 5080,
    SpvExecutionModeStencilRefLessFrontAMD = 5081,
@@ -226,6 +231,8 @@ typedef enum SpvStorageClass_ {
    SpvStorageClassImage = 11,
    SpvStorageClassStorageBuffer = 12,
    SpvStorageClassTileImageEXT = 4172,
+    SpvStorageClassNodePayloadAMDX = 5068,
+    SpvStorageClassNodeOutputPayloadAMDX = 5076,
    SpvStorageClassCallableDataKHR = 5328,
    SpvStorageClassCallableDataNV = 5328,
    SpvStorageClassIncomingCallableDataKHR = 5329,
@@ -526,6 +533,10 @@ typedef enum SpvDecoration_ {
    SpvDecorationWeightTextureQCOM = 4487,
    SpvDecorationBlockMatchTextureQCOM = 4488,
    SpvDecorationExplicitInterpAMD = 4999,
+    SpvDecorationNodeSharesPayloadLimitsWithAMDX = 5019,
+    SpvDecorationNodeMaxPayloadsAMDX = 5020,
+    SpvDecorationTrackFinishWritingAMDX = 5078,
+    SpvDecorationPayloadNodeNameAMDX = 5091,
    SpvDecorationOverrideCoverageNV = 5248,
    SpvDecorationPassthroughNV = 5250,
    SpvDecorationViewportRelativeNV = 5252,
@@ -593,6 +604,9 @@ typedef enum SpvDecoration_ {
    SpvDecorationSingleElementVectorINTEL = 6085,
    SpvDecorationVectorComputeCallableFunctionINTEL = 6087,
    SpvDecorationMediaBlockIOINTEL = 6140,
+    SpvDecorationInitModeINTEL = 6147,
+    SpvDecorationImplementInRegisterMapINTEL = 6148,
+    SpvDecorationHostAccessINTEL = 6168,
    SpvDecorationFPMaxErrorDecorationINTEL = 6170,
    SpvDecorationLatencyControlLabelINTEL = 6172,
    SpvDecorationLatencyControlConstraintINTEL = 6173,
@@ -680,6 +694,8 @@ typedef enum SpvBuiltIn_ {
    SpvBuiltInBaryCoordSmoothSampleAMD = 4997,
    SpvBuiltInBaryCoordPullModelAMD = 4998,
    SpvBuiltInFragStencilRefEXT = 5014,
+    SpvBuiltInCoalescedInputCountAMDX = 5021,
+    SpvBuiltInShaderIndexAMDX = 5073,
    SpvBuiltInViewportMaskNV = 5253,
    SpvBuiltInSecondaryPositionNV = 5257,
    SpvBuiltInSecondaryViewportMaskNV = 5258,
@@ -1048,6 +1064,7 @@ typedef enum SpvCapability_ {
    SpvCapabilityImageReadWriteLodAMD = 5015,
    SpvCapabilityInt64ImageEXT = 5016,
    SpvCapabilityShaderClockKHR = 5055,
+    SpvCapabilityShaderEnqueueAMDX = 5067,
    SpvCapabilitySampleMaskOverrideCoverageNV = 5249,
    SpvCapabilityGeometryShaderPassthroughNV = 5251,
    SpvCapabilityShaderViewportIndexLayerEXT = 5254,
@@ -1173,7 +1190,9 @@ typedef enum SpvCapability_ {
    SpvCapabilityDebugInfoModuleINTEL = 6114,
    SpvCapabilityBFloat16ConversionINTEL = 6115,
    SpvCapabilitySplitBarrierINTEL = 6141,
+    SpvCapabilityGlobalVariableFPGADecorationsINTEL = 6146,
    SpvCapabilityFPGAKernelAttributesv2INTEL = 6161,
+    SpvCapabilityGlobalVariableHostAccessINTEL = 6167,
    SpvCapabilityFPMaxErrorINTEL = 6169,
    SpvCapabilityFPGALatencyControlINTEL = 6171,
    SpvCapabilityFPGAArgumentInterfacesINTEL = 6174,
@@ -1315,6 +1334,20 @@ typedef enum SpvCooperativeMatrixUse_ {
    SpvCooperativeMatrixUseMax = 0x7fffffff,
 } SpvCooperativeMatrixUse;

+typedef enum SpvInitializationModeQualifier_ {
+    SpvInitializationModeQualifierInitOnDeviceReprogramINTEL = 0,
+    SpvInitializationModeQualifierInitOnDeviceResetINTEL = 1,
+    SpvInitializationModeQualifierMax = 0x7fffffff,
+} SpvInitializationModeQualifier;
+
+typedef enum SpvHostAccessQualifier_ {
+    SpvHostAccessQualifierNoneINTEL = 0,
+    SpvHostAccessQualifierReadINTEL = 1,
+    SpvHostAccessQualifierWriteINTEL = 2,
+    SpvHostAccessQualifierReadWriteINTEL = 3,
+    SpvHostAccessQualifierMax = 0x7fffffff,
+} SpvHostAccessQualifier;
+
 typedef enum SpvOp_ {
    SpvOpNop = 0,
    SpvOpUndef = 1,
@@ -1715,6 +1748,9 @@ typedef enum SpvOp_ {
    SpvOpFragmentMaskFetchAMD = 5011,
    SpvOpFragmentFetchAMD = 5012,
    SpvOpReadClockKHR = 5056,
+    SpvOpFinalizeNodePayloadsAMDX = 5075,
+    SpvOpFinishWritingNodePayloadAMDX = 5078,
+    SpvOpInitializeNodePayloadsAMDX = 5090,
    SpvOpHitObjectRecordHitMotionNV = 5249,
    SpvOpHitObjectRecordHitWithIndexMotionNV = 5250,
    SpvOpHitObjectRecordMissMotionNV = 5251,
@@ -2438,6 +2474,9 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy
    case SpvOpFragmentMaskFetchAMD: *hasResult = true; *hasResultType = true; break;
    case SpvOpFragmentFetchAMD: *hasResult = true; *hasResultType = true; break;
    case SpvOpReadClockKHR: *hasResult = true; *hasResultType = true; break;
+    case SpvOpFinalizeNodePayloadsAMDX: *hasResult = false; *hasResultType = false; break;
+    case SpvOpFinishWritingNodePayloadAMDX: *hasResult = true; *hasResultType = true; break;
+    case SpvOpInitializeNodePayloadsAMDX: *hasResult = false; *hasResultType = false; break;
    case SpvOpHitObjectRecordHitMotionNV: *hasResult = false; *hasResultType = false; break;
    case SpvOpHitObjectRecordHitWithIndexMotionNV: *hasResult = false; *hasResultType = false; break;
    case SpvOpHitObjectRecordMissMotionNV: *hasResult = false; *hasResultType = false; break;
--- a/3rdparty/spirv-headers/include/spirv/unified1/spirv.hpp11
+++ b/3rdparty/spirv-headers/include/spirv/unified1/spirv.hpp11
@@ -171,6 +171,11 @@ enum class ExecutionMode : unsigned {
    RoundingModeRTZ = 4463,
    EarlyAndLateFragmentTestsAMD = 5017,
    StencilRefReplacingEXT = 5027,
+    CoalescingAMDX = 5069,
+    MaxNodeRecursionAMDX = 5071,
+    StaticNumWorkgroupsAMDX = 5072,
+    ShaderIndexAMDX = 5073,
+    MaxNumWorkgroupsAMDX = 5077,
    StencilRefUnchangedFrontAMD = 5079,
    StencilRefGreaterFrontAMD = 5080,
    StencilRefLessFrontAMD = 5081,
@@ -222,6 +227,8 @@ enum class StorageClass : unsigned {
    Image = 11,
    StorageBuffer = 12,
    TileImageEXT = 4172,
+    NodePayloadAMDX = 5068,
+    NodeOutputPayloadAMDX = 5076,
    CallableDataKHR = 5328,
    CallableDataNV = 5328,
    IncomingCallableDataKHR = 5329,
@@ -522,6 +529,10 @@ enum class Decoration : unsigned {
    WeightTextureQCOM = 4487,
    BlockMatchTextureQCOM = 4488,
    ExplicitInterpAMD = 4999,
+    NodeSharesPayloadLimitsWithAMDX = 5019,
+    NodeMaxPayloadsAMDX = 5020,
+    TrackFinishWritingAMDX = 5078,
+    PayloadNodeNameAMDX = 5091,
    OverrideCoverageNV = 5248,
    PassthroughNV = 5250,
    ViewportRelativeNV = 5252,
@@ -589,6 +600,9 @@ enum class Decoration : unsigned {
    SingleElementVectorINTEL = 6085,
    VectorComputeCallableFunctionINTEL = 6087,
    MediaBlockIOINTEL = 6140,
+    InitModeINTEL = 6147,
+    ImplementInRegisterMapINTEL = 6148,
+    HostAccessINTEL = 6168,
    FPMaxErrorDecorationINTEL = 6170,
    LatencyControlLabelINTEL = 6172,
    LatencyControlConstraintINTEL = 6173,
@@ -676,6 +690,8 @@ enum class BuiltIn : unsigned {
    BaryCoordSmoothSampleAMD = 4997,
    BaryCoordPullModelAMD = 4998,
    FragStencilRefEXT = 5014,
+    CoalescedInputCountAMDX = 5021,
+    ShaderIndexAMDX = 5073,
    ViewportMaskNV = 5253,
    SecondaryPositionNV = 5257,
    SecondaryViewportMaskNV = 5258,
@@ -1044,6 +1060,7 @@ enum class Capability : unsigned {
    ImageReadWriteLodAMD = 5015,
    Int64ImageEXT = 5016,
    ShaderClockKHR = 5055,
+    ShaderEnqueueAMDX = 5067,
    SampleMaskOverrideCoverageNV = 5249,
    GeometryShaderPassthroughNV = 5251,
    ShaderViewportIndexLayerEXT = 5254,
@@ -1169,7 +1186,9 @@ enum class Capability : unsigned {
    DebugInfoModuleINTEL = 6114,
    BFloat16ConversionINTEL = 6115,
    SplitBarrierINTEL = 6141,
+    GlobalVariableFPGADecorationsINTEL = 6146,
    FPGAKernelAttributesv2INTEL = 6161,
+    GlobalVariableHostAccessINTEL = 6167,
    FPMaxErrorINTEL = 6169,
    FPGALatencyControlINTEL = 6171,
    FPGAArgumentInterfacesINTEL = 6174,
@@ -1311,6 +1330,20 @@ enum class CooperativeMatrixUse : unsigned {
    Max = 0x7fffffff,
 };

+enum class InitializationModeQualifier : unsigned {
+    InitOnDeviceReprogramINTEL = 0,
+    InitOnDeviceResetINTEL = 1,
+    Max = 0x7fffffff,
+};
+
+enum class HostAccessQualifier : unsigned {
+    NoneINTEL = 0,
+    ReadINTEL = 1,
+    WriteINTEL = 2,
+    ReadWriteINTEL = 3,
+    Max = 0x7fffffff,
+};
+
 enum class Op : unsigned {
    OpNop = 0,
    OpUndef = 1,
@@ -1711,6 +1744,9 @@ enum class Op : unsigned {
    OpFragmentMaskFetchAMD = 5011,
    OpFragmentFetchAMD = 5012,
    OpReadClockKHR = 5056,
+    OpFinalizeNodePayloadsAMDX = 5075,
+    OpFinishWritingNodePayloadAMDX = 5078,
+    OpInitializeNodePayloadsAMDX = 5090,
    OpHitObjectRecordHitMotionNV = 5249,
    OpHitObjectRecordHitWithIndexMotionNV = 5250,
    OpHitObjectRecordMissMotionNV = 5251,
@@ -2434,6 +2470,9 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
    case Op::OpFragmentMaskFetchAMD: *hasResult = true; *hasResultType = true; break;
    case Op::OpFragmentFetchAMD: *hasResult = true; *hasResultType = true; break;
    case Op::OpReadClockKHR: *hasResult = true; *hasResultType = true; break;
+    case Op::OpFinalizeNodePayloadsAMDX: *hasResult = false; *hasResultType = false; break;
+    case Op::OpFinishWritingNodePayloadAMDX: *hasResult = true; *hasResultType = true; break;
+    case Op::OpInitializeNodePayloadsAMDX: *hasResult = false; *hasResultType = false; break;
    case Op::OpHitObjectRecordHitMotionNV: *hasResult = false; *hasResultType = false; break;
    case Op::OpHitObjectRecordHitWithIndexMotionNV: *hasResult = false; *hasResultType = false; break;
    case Op::OpHitObjectRecordMissMotionNV: *hasResult = false; *hasResultType = false; break;
--- a/3rdparty/spirv-headers/include/spirv/unified1/spirv.json
+++ b/3rdparty/spirv-headers/include/spirv/unified1/spirv.json
@@ -190,6 +190,11 @@
                    "RoundingModeRTZ": 4463,
                    "EarlyAndLateFragmentTestsAMD": 5017,
                    "StencilRefReplacingEXT": 5027,
+                    "CoalescingAMDX": 5069,
+                    "MaxNodeRecursionAMDX": 5071,
+                    "StaticNumWorkgroupsAMDX": 5072,
+                    "ShaderIndexAMDX": 5073,
+                    "MaxNumWorkgroupsAMDX": 5077,
                    "StencilRefUnchangedFrontAMD": 5079,
                    "StencilRefGreaterFrontAMD": 5080,
                    "StencilRefLessFrontAMD": 5081,
@@ -244,6 +249,8 @@
                    "Image": 11,
                    "StorageBuffer": 12,
                    "TileImageEXT": 4172,
+                    "NodePayloadAMDX": 5068,
+                    "NodeOutputPayloadAMDX": 5076,
                    "CallableDataKHR": 5328,
                    "CallableDataNV": 5328,
                    "IncomingCallableDataKHR": 5329,
@@ -548,6 +555,10 @@
                    "WeightTextureQCOM": 4487,
                    "BlockMatchTextureQCOM": 4488,
                    "ExplicitInterpAMD": 4999,
+                    "NodeSharesPayloadLimitsWithAMDX": 5019,
+                    "NodeMaxPayloadsAMDX": 5020,
+                    "TrackFinishWritingAMDX": 5078,
+                    "PayloadNodeNameAMDX": 5091,
                    "OverrideCoverageNV": 5248,
                    "PassthroughNV": 5250,
                    "ViewportRelativeNV": 5252,
@@ -615,6 +626,9 @@
                    "SingleElementVectorINTEL": 6085,
                    "VectorComputeCallableFunctionINTEL": 6087,
                    "MediaBlockIOINTEL": 6140,
+                    "InitModeINTEL": 6147,
+                    "ImplementInRegisterMapINTEL": 6148,
+                    "HostAccessINTEL": 6168,
                    "FPMaxErrorDecorationINTEL": 6170,
                    "LatencyControlLabelINTEL": 6172,
                    "LatencyControlConstraintINTEL": 6173,
@@ -705,6 +719,8 @@
                    "BaryCoordSmoothSampleAMD": 4997,
                    "BaryCoordPullModelAMD": 4998,
                    "FragStencilRefEXT": 5014,
+                    "CoalescedInputCountAMDX": 5021,
+                    "ShaderIndexAMDX": 5073,
                    "ViewportMaskNV": 5253,
                    "SecondaryPositionNV": 5257,
                    "SecondaryViewportMaskNV": 5258,
@@ -1024,6 +1040,7 @@
                    "ImageReadWriteLodAMD": 5015,
                    "Int64ImageEXT": 5016,
                    "ShaderClockKHR": 5055,
+                    "ShaderEnqueueAMDX": 5067,
                    "SampleMaskOverrideCoverageNV": 5249,
                    "GeometryShaderPassthroughNV": 5251,
                    "ShaderViewportIndexLayerEXT": 5254,
@@ -1149,7 +1166,9 @@
                    "DebugInfoModuleINTEL": 6114,
                    "BFloat16ConversionINTEL": 6115,
                    "SplitBarrierINTEL": 6141,
+                    "GlobalVariableFPGADecorationsINTEL": 6146,
                    "FPGAKernelAttributesv2INTEL": 6161,
+                    "GlobalVariableHostAccessINTEL": 6167,
                    "FPMaxErrorINTEL": 6169,
                    "FPGALatencyControlINTEL": 6171,
                    "FPGAArgumentInterfacesINTEL": 6174,
@@ -1297,6 +1316,26 @@
                    "MatrixAccumulatorKHR": 2
                }
            },
+            {
+                "Name": "InitializationModeQualifier",
+                "Type": "Value",
+                "Values":
+                {
+                    "InitOnDeviceReprogramINTEL": 0,
+                    "InitOnDeviceResetINTEL": 1
+                }
+            },
+            {
+                "Name": "HostAccessQualifier",
+                "Type": "Value",
+                "Values":
+                {
+                    "NoneINTEL": 0,
+                    "ReadINTEL": 1,
+                    "WriteINTEL": 2,
+                    "ReadWriteINTEL": 3
+                }
+            },
            {
                "Name": "Op",
                "Type": "Value",
@@ -1701,6 +1740,9 @@
                    "OpFragmentMaskFetchAMD": 5011,
                    "OpFragmentFetchAMD": 5012,
                    "OpReadClockKHR": 5056,
+                    "OpFinalizeNodePayloadsAMDX": 5075,
+                    "OpFinishWritingNodePayloadAMDX": 5078,
+                    "OpInitializeNodePayloadsAMDX": 5090,
                    "OpHitObjectRecordHitMotionNV": 5249,
                    "OpHitObjectRecordHitWithIndexMotionNV": 5250,
                    "OpHitObjectRecordMissMotionNV": 5251,